724
7 Countermeasures Against Hardware Trojans
17. J.B. Webb, Methods for securing the integrity of FPGA configurations. Dis. Virginia
Polytechnic Institute and State University (2006)
18. S. Trimberger, Trusted design in FPGAs, in Design Automation Conference, 2007. DAC’07.
44th ACM/IEEE. IEEE (2007), pp. 5–8
19. A. Baumgarten, A. Tyagi, J. Zambreno, Preventing IC piracy using reconfigurable logic
barriers. IEEE Des. Test Comput. 27(1), 66–75 (2010)
20. T. Huffmire et al., Moats and drawbridges: an isolation primitive for reconfigurable hardware
based systems, in Security and Privacy, 2007. SP’07. IEEE Symposium. IEEE (2007), pp. 81–
295
21. M.L. Silva, J.C. Ferreira, Creation of partial FPGA configurations at run-time, in Digital
System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference.
IEEE (2010), pp. 80–87
22. B. Newgard, C. Hoffman, Using multiple processors in a single reconfigurable fabric for
high-assurance applications, in Hardware-Oriented Security and Trust (HOST), 2010 IEEE
International Symposium on. IEEE (2010), pp. 25–29
23. D. McIntyre et al., Dynamic evaluation of hardware trust, in Hardware-Oriented Security and
Trust, 2009. HOST 09. IEEE International Workshop. IEEE (2009), pp. 108–111
24. S.S. Kumar et al., The butterfly PUF protecting IP on every FPGA, in Hardware-Oriented
Security and Trust, 2008. HOST 2008. IEEE International Workshop. IEEE (2008) pp. 67–70
25. G. Trouessin et al., Improvement of data processing security by means of fault tolerance,
in Proceedings Of The 14th National Computer Security Conference (NCSC’14) (1991.),
pp. 295–304
26. A. Shamir, How to share a secret. Commun. ACM 22 (11), 612–613 (1979)
27. E. Kuznetsov, A. Saurov, Hardware trojans. Part 2: prevention and detection methods.
Nanoindustry 1(71), 30–40 (2017)
28. K. Jarvinen et al., Garbled circuits for leakage-resilience: hardware implementation and evaluation of one-time programs, in Cryptographic Hardware and Embedded Systems, CHES
2010, (Springer Berlin Heidelberg, 2010), pp. 383–397
29. L.-W. Kim, J.D. Villasenor, C.K. Koc, A trojan-resistant system-on-chip bus architecture.
Electrical Engineering Department, University of California, Los Angeles 2 Computer Science
Department, University of California, Santa Babara May 15 (2009)
30. F. Wolff, C. Papachristou, S. Bhunia, R. Chakraborty, Towards trojan-free trusted ICs: problem
analysis and detection scheme, in Proceedings, Design Automation and Test in Europe
(DATE’09) (Munich, Germany, March 10—14, 2008), pp. 1362—1365
31. Y. Jin, Y. Makris, Hardware trojan detection using path delay fingerprint, in IEEE International
Workshop on Hardware-Oriented Security and Trust (HOST’08) (2008), pp. 51–57
32. X. Wang. Hardware trojan attacks: threat analysis and low-cost countermeasures through
golden-free detection and secure design, January (2014)
33. DARPA. TRUST, in Integrated Circuits (TIC) (2007). http://www.darpa.mil/MTO/solicitat
ions/baa07-24
34. R.S. Chakraborty, S. Narasimhan, S. Bhunia, Hardware trojan: threats and emerging solutions,
in High-Level Design Verification and Test Workshop (2009)
35. L. Lin, W. Burleson, C. Parr, MOLES: malicious o_-chip leakage enabled by side- channels.
Int. Conf. Comput.-Aided Des (2009)
36. Y. Jin, Y. Makris, Hardware trojans in wireless cryptographic ICs. IEEE Des. Test Comput.
27(1), 26–35 (2010)
37. Cyber Security Awareness Week ESC. http://www.poly.edu/csaw-embedded
38. X. Wang, S. Narasimhan, A. Krishna, T. Mal-Sarkar, S. Bhunia, Sequential hardware
trojan: side-channel aware design and placement, in IEEE 29th International Conference
on Computer Design (ICCD) (2011)
39. A. Maiti, J. Casarona, L. McHale, P. Schaumont, A large scale characterization of RO-PUF,
in Proc. IEEE Intl. Workshop on Hardware-Oriented Security and Trust (HOST) (2010)
40. S. Narasimhan, X. Wang, D. Du, R.S. Chakraborty, S. Bhunia, TeSR: a robust temporal
self-referencing approach for hardware trojan detection, in Proc. IEEE Intl. Workshop on
Hardware-Oriented Security and Trust (HOST) (2011)
7 Countermeasures Against Hardware Trojans
17. J.B. Webb, Methods for securing the integrity of FPGA configurations. Dis. Virginia
Polytechnic Institute and State University (2006)
18. S. Trimberger, Trusted design in FPGAs, in Design Automation Conference, 2007. DAC’07.
44th ACM/IEEE. IEEE (2007), pp. 5–8
19. A. Baumgarten, A. Tyagi, J. Zambreno, Preventing IC piracy using reconfigurable logic
barriers. IEEE Des. Test Comput. 27(1), 66–75 (2010)
20. T. Huffmire et al., Moats and drawbridges: an isolation primitive for reconfigurable hardware
based systems, in Security and Privacy, 2007. SP’07. IEEE Symposium. IEEE (2007), pp. 81–
295
21. M.L. Silva, J.C. Ferreira, Creation of partial FPGA configurations at run-time, in Digital
System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference.
IEEE (2010), pp. 80–87
22. B. Newgard, C. Hoffman, Using multiple processors in a single reconfigurable fabric for
high-assurance applications, in Hardware-Oriented Security and Trust (HOST), 2010 IEEE
International Symposium on. IEEE (2010), pp. 25–29
23. D. McIntyre et al., Dynamic evaluation of hardware trust, in Hardware-Oriented Security and
Trust, 2009. HOST 09. IEEE International Workshop. IEEE (2009), pp. 108–111
24. S.S. Kumar et al., The butterfly PUF protecting IP on every FPGA, in Hardware-Oriented
Security and Trust, 2008. HOST 2008. IEEE International Workshop. IEEE (2008) pp. 67–70
25. G. Trouessin et al., Improvement of data processing security by means of fault tolerance,
in Proceedings Of The 14th National Computer Security Conference (NCSC’14) (1991.),
pp. 295–304
26. A. Shamir, How to share a secret. Commun. ACM 22 (11), 612–613 (1979)
27. E. Kuznetsov, A. Saurov, Hardware trojans. Part 2: prevention and detection methods.
Nanoindustry 1(71), 30–40 (2017)
28. K. Jarvinen et al., Garbled circuits for leakage-resilience: hardware implementation and evaluation of one-time programs, in Cryptographic Hardware and Embedded Systems, CHES
2010, (Springer Berlin Heidelberg, 2010), pp. 383–397
29. L.-W. Kim, J.D. Villasenor, C.K. Koc, A trojan-resistant system-on-chip bus architecture.
Electrical Engineering Department, University of California, Los Angeles 2 Computer Science
Department, University of California, Santa Babara May 15 (2009)
30. F. Wolff, C. Papachristou, S. Bhunia, R. Chakraborty, Towards trojan-free trusted ICs: problem
analysis and detection scheme, in Proceedings, Design Automation and Test in Europe
(DATE’09) (Munich, Germany, March 10—14, 2008), pp. 1362—1365
31. Y. Jin, Y. Makris, Hardware trojan detection using path delay fingerprint, in IEEE International
Workshop on Hardware-Oriented Security and Trust (HOST’08) (2008), pp. 51–57
32. X. Wang. Hardware trojan attacks: threat analysis and low-cost countermeasures through
golden-free detection and secure design, January (2014)
33. DARPA. TRUST, in Integrated Circuits (TIC) (2007). http://www.darpa.mil/MTO/solicitat
ions/baa07-24
34. R.S. Chakraborty, S. Narasimhan, S. Bhunia, Hardware trojan: threats and emerging solutions,
in High-Level Design Verification and Test Workshop (2009)
35. L. Lin, W. Burleson, C. Parr, MOLES: malicious o_-chip leakage enabled by side- channels.
Int. Conf. Comput.-Aided Des (2009)
36. Y. Jin, Y. Makris, Hardware trojans in wireless cryptographic ICs. IEEE Des. Test Comput.
27(1), 26–35 (2010)
37. Cyber Security Awareness Week ESC. http://www.poly.edu/csaw-embedded
38. X. Wang, S. Narasimhan, A. Krishna, T. Mal-Sarkar, S. Bhunia, Sequential hardware
trojan: side-channel aware design and placement, in IEEE 29th International Conference
on Computer Design (ICCD) (2011)
39. A. Maiti, J. Casarona, L. McHale, P. Schaumont, A large scale characterization of RO-PUF,
in Proc. IEEE Intl. Workshop on Hardware-Oriented Security and Trust (HOST) (2010)
40. S. Narasimhan, X. Wang, D. Du, R.S. Chakraborty, S. Bhunia, TeSR: a robust temporal
self-referencing approach for hardware trojan detection, in Proc. IEEE Intl. Workshop on
Hardware-Oriented Security and Trust (HOST) (2011)