7.8 Methods for Controlling Safety …
723
part of the chip similarly to [128, 129]. This method uses the so-called logical
barriers with variable configuration. As mentioned above, the advantage of such
programmable parts of on-chip memory is storage of a part of design documentation
with the IP rights holder. The disadvantage of this method is the additional overhead
costs of the processes and masks used to implement these programmable components
in the ASIC.
Due to the limited volume of the book, we refer interested readers to specific
works [125, 127, 133–135] for a more detailed description of other proposed extrinsic
metering methods.
References
1. E. Kuznetsov, A. Saurov, Hardware trojans. Part 4: software and hardware countermeasures.
Nanoindustry 2, 42 (2017)
2. E. Kuznetsov, A. Saurov, Hardware trojans. Part 1: new threats to cyber security. Nanoindustry
7(69), 16–25 (2016)
3. E. Kuznetsov, A. Saurov, Hardware trojans. Part 3: examples of implementation, means of
introduction and activation. Nanoindustry 8(70), 12–21 (2016)
4. A. Waksman, S. Sethumadhavan, Silencing hardware backdoors. Security and Privacy (SP),
2011 IEEE Symposium. IEEE, 49–63 (2011)
5. C. Gentry, Computing arbitrary functions of encrypted data. Communications of the ACM
53(3), 97–105 (2010)
6. R.S. Chakraborty, S. Narasimhan, S. Bhunia, Hardware trojan: threats and emerging solutions,
in High Level Design Validation and Test Workshop, 2009. HLDVT 2009. IEEE International.
IEEE (2009), 166–171
7. LW. Kim, J.D. Villasenor, C.K. Koc, A trojan-resistant system-on-chip bus architecture, in
Military Communications Conference, 2009. MIL-COM 2009. IEEE (2009), pp. 1–6
8. A. Das et al., Detecting/preventing information leakage on the memory bus due to malicious
hardware, in Proceedings of the Conference on Design, Automation and Test in Europe.
European Design and Automation Association (2010), pp. 861–866
9. G. Bloom et al., Providing secure execution environments with a last line of defense against
trojan circuit attacks. Comput. Sec. 28(7), 660–669 (2009)
10. G.E. Suh et al., AEGIS: architecture for tamper-evident and tamper-resistant processing, in
Proceedings of the 17th annual international conference on Supercomputing. ACM (2003),
pp. 160–171
11. M. Anderson, C. North, K. Yiu, Towards countering the rise of the silicon trojan. DSTO
Technical Report DSTOTR-2220. DSTO Information Sciences Laboratory (2008)
12. M. Hicks et al., Overcoming an untrusted computing base: detecting and removing malicious
hardware automatically, in Security and Privacy (SP), 2010 IEEE Symposium. IEEE (2010),
pp. 159–172
13. A. Belous, V. Saladukha, S. Shvedau, in Space Microelectronics, vol. 1, 2 (Artech House,
London, 2017). ISBN: 9781630812577
14. C. Sturton et al., Defeating UCI: building stealthy and malicious hardware, in Security and
Privacy (SP), 2011 IEEE Symposium. IEEE (2011), pp. 64–77
15. M. Abramovici, P. Bradley, Integrated circuit w security: new threats and solutions, in Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research:
Cyber Security and Information Intelligence Challenges and Strategies. ACM, p. 55
16. D.Y. Deng, A.H. Chan, G.E. Suh, Hardware authentication leveraging performance limits in
detailed simulations and emulations, in Proceedings of the 46th Annual Design Automation
Conference. ACM (2009) 682–687
723
part of the chip similarly to [128, 129]. This method uses the so-called logical
barriers with variable configuration. As mentioned above, the advantage of such
programmable parts of on-chip memory is storage of a part of design documentation
with the IP rights holder. The disadvantage of this method is the additional overhead
costs of the processes and masks used to implement these programmable components
in the ASIC.
Due to the limited volume of the book, we refer interested readers to specific
works [125, 127, 133–135] for a more detailed description of other proposed extrinsic
metering methods.
References
1. E. Kuznetsov, A. Saurov, Hardware trojans. Part 4: software and hardware countermeasures.
Nanoindustry 2, 42 (2017)
2. E. Kuznetsov, A. Saurov, Hardware trojans. Part 1: new threats to cyber security. Nanoindustry
7(69), 16–25 (2016)
3. E. Kuznetsov, A. Saurov, Hardware trojans. Part 3: examples of implementation, means of
introduction and activation. Nanoindustry 8(70), 12–21 (2016)
4. A. Waksman, S. Sethumadhavan, Silencing hardware backdoors. Security and Privacy (SP),
2011 IEEE Symposium. IEEE, 49–63 (2011)
5. C. Gentry, Computing arbitrary functions of encrypted data. Communications of the ACM
53(3), 97–105 (2010)
6. R.S. Chakraborty, S. Narasimhan, S. Bhunia, Hardware trojan: threats and emerging solutions,
in High Level Design Validation and Test Workshop, 2009. HLDVT 2009. IEEE International.
IEEE (2009), 166–171
7. LW. Kim, J.D. Villasenor, C.K. Koc, A trojan-resistant system-on-chip bus architecture, in
Military Communications Conference, 2009. MIL-COM 2009. IEEE (2009), pp. 1–6
8. A. Das et al., Detecting/preventing information leakage on the memory bus due to malicious
hardware, in Proceedings of the Conference on Design, Automation and Test in Europe.
European Design and Automation Association (2010), pp. 861–866
9. G. Bloom et al., Providing secure execution environments with a last line of defense against
trojan circuit attacks. Comput. Sec. 28(7), 660–669 (2009)
10. G.E. Suh et al., AEGIS: architecture for tamper-evident and tamper-resistant processing, in
Proceedings of the 17th annual international conference on Supercomputing. ACM (2003),
pp. 160–171
11. M. Anderson, C. North, K. Yiu, Towards countering the rise of the silicon trojan. DSTO
Technical Report DSTOTR-2220. DSTO Information Sciences Laboratory (2008)
12. M. Hicks et al., Overcoming an untrusted computing base: detecting and removing malicious
hardware automatically, in Security and Privacy (SP), 2010 IEEE Symposium. IEEE (2010),
pp. 159–172
13. A. Belous, V. Saladukha, S. Shvedau, in Space Microelectronics, vol. 1, 2 (Artech House,
London, 2017). ISBN: 9781630812577
14. C. Sturton et al., Defeating UCI: building stealthy and malicious hardware, in Security and
Privacy (SP), 2011 IEEE Symposium. IEEE (2011), pp. 64–77
15. M. Abramovici, P. Bradley, Integrated circuit w security: new threats and solutions, in Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research:
Cyber Security and Information Intelligence Challenges and Strategies. ACM, p. 55
16. D.Y. Deng, A.H. Chan, G.E. Suh, Hardware authentication leveraging performance limits in
detailed simulations and emulations, in Proceedings of the 46th Annual Design Automation
Conference. ACM (2009) 682–687