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41. X. Wang, T. Mal-Sarkar, A. Krishna, S. Narasimhan, S. Bhunia, Software exploitable hardware trojans in embedded processor, in IEEE International Symposium on Defect and Fault
Tolerance in VLSI and Nanotechnology Systems (DFT) (2012)
42. M. Tehranipoor, F. Koushanfar, A survey of hardware Trojan taxonomy and detection. IEEE
Des. Test Comput. 27(1), 10–25 (2010)
43. Y Jin, Y. Makris. Hardware trojan detection using path delay finngerprint, HOST (2008)
44. S.T. King et al., Designing and implementing malicious hardware, in USENIX Workshop on
LEET (2008)
45. R.R. Rivest, The RC5 Encryption Algorithm, FSE (1994)
46. R. Karri, J. Rajendran, K. Rosenfeld, M. Tehranipoor. Toward trusted hardware: Identifying
and classifying hardware Trojans. IEEE Computer Magazine (2010)
47. A.R. Alameldeen, D.A. Wood, in Adaptive Cache Compression for High Performance
Processors. ISCA (2004)
48. H. Asadi et al., in Reliability Tradeoffs in Design of Cache Memories. Workshop on
Architectural Reliability (2005)
49. A.J. van de Goor, Using March Tests to Test SRAMs. IEEE Des. Test Comput. March (1993)
50. S. Hamdioui, A.J. van de Goor, An Experimental Analysis of Spot Defects in SRAMs: Realistic
Fault Models and Tests. ATS (2000)
51. S. Hamdioui et al., in Memory Test Experiment: Indistrial Results and Data, IEE Proceedings
(2006)
52. Predictive Technology Model. http://www.eas.asu.edu/_ptm/
53. Y. Lu et al., FPGA implementation and analysis of random delay insertion countermeasure
against DPA, in Proceedings of the International Conference on ICECE Technology (FTP08)
(2008)
54. D. Hely et al., Scan design and secure chip, in IEEE Intl. On-Line Testing Symposium (2004)
55. Synopsys Veri_cation IP: http://www.synopsys.com/Tools/Verification/FunctionalVeri_cat
ion/Veri_cationIP/Pages/default.aspx
56. P. Bernardi et al., Exploiting an I-IP for in-_eld SoC test. DFT (2004)
57. S. Narasimhan et al., Improving IC security against trojan attacks through integration of
security monitors. IEEE Des. Test Comput. Spec. Iss. Smart Sili. (2012)
58. Intellitech Test-IP Product Family: http://www.intellitech.com/-products/boundaryscantes
t.asp
59. S. Tabatabaei et al., Embedded timing analysis: a SoC infrastructure. IEEE Des. Test Comput.
(2002)
60. E. Dupont et al., Embedded robustness IPs for transient-error-free ICs. IEEE Des. Test
Comput. (2002)
61. J. Bordelon et al., A strategy for mixed-signal yield improvement. IEEE Des. Test Comput.
(2002)
62. Y. Zorian., Guest editor’s introduction: what is infrastructure IP? IEEE Des. Test Comput
(2002)
63. F. DaSilva et al., Overview of the IEEE P1500 standard. ITC (2003)
64. IEEE 1500 Embedded Core Test: http://grouper.ieee.org/groups/1500/
65. IEEE 1450.6 Core Test Language (CTL): http://grouper.ieee.org/groups/ctl/
66. D.D. Josephson et al., Debug methodology for the McKinley processor. ITC (2001)
67. B. Yang et al., Secure scan: a design-for-test architecture for crypto chips. DAC (2005)
68. J. Lee et al., Securing scan design using lock & key technique. DFT (2005)
69. S. Paul et al., VIm-scan: a low overhead scan design approach for protection of secret key in
scan-based secure chips. VTS (2007)
70. Q. Xu et al., Delay fault testing of core-based systems-on-a-chip. Date (2003)
71. X. Wang et al., Role of power grid in side channel attack and power-grid-aware secure design.
DAC (2013)
72. Towards a Hardware Trojan Detection Cycle, Adrian Dabrowski, Heidelinde Hobel, Johanna
Ullrich, Katharina Krombholz, Edgar Weippl SBA Research, Vienna, Austria, E-mail:
(firstletterfirstname) (lastname)@sba-research.org