670
7 Countermeasures Against Hardware Trojans
Defined user port for
testing
Wrapper parallel
input
Wrapper serial
input
Required wrapper
serial port (WSP)
Additional wrapper parallel port
(WPP)
Wrapper parallel
port
Wrapper serial
port
Standard port for
connection
Serial wrapper
control
Functional
outputs
Functional inputs
Functional
outputs
Functional inputs
Testing activators
CORE
CORE
Fig. 7.10 Structure of the IEEE 1500 standard: transit terminals of the core wrapper (a); mandatory
wrapper components (b) [68]
testing language (CTL) [65] used to described information about the tested core.
In order to satisfy requirements of the standard, each IP core in SoC shall have its
test wrapper. The wrapper is usually one cell of the so-called boundary register for
each functional I/O port, where all cells of this boundary register are called a wrapper
boundary register (WBR). It also comprises a wrapper instruction register (WIR) and
a wrapper bypass register (WBR). Figure 7.10 shows the structure of the high-level
core wrapper interface and mandatory components of the core wrapper.
By configuring functional WIR cores in SoC, it is possible to connect all WBR in
series by various means in order to ensure four main modes of SoC operation: normal
inward mode for core inspection, outward mode for interconnection inspection, and
bypass mode.
Test access to the cores embedded in SoC is ensured by core wrapper and the
so-called test access mechanism (TAM) embedded in the microcircuit. Figure 7.10a
shows two methods of accessing cores: mandatory access is provided through the
Wrapper Serial Ports (WSP), and additional access is provided through Wrapper
Parallel Ports (WPP). WSP provides a single-bit port for test data (WSI/WSO) with
test clocking (WRCK) and control signals (WSC), while WPP has a higher capacity
to ensure more effective implementation of tests.
It should be noted that the IEEE Std. 1500 does not involve using the WPP port;
therefore, the core provider is responsibe for designing this port. Due to this reason,
IIPS in the cited work [33] was designed using WSP exclusively. Here we also do
not discuss various architecture variants of a parallel TAM. If a certain structure
of parallel TAM is presented, scaling of the security test from the core level to the
SoC level can follow the same methodology as scaling of a traditional core test with
access to parallel testing.
7 Countermeasures Against Hardware Trojans
Defined user port for
testing
Wrapper parallel
input
Wrapper serial
input
Required wrapper
serial port (WSP)
Additional wrapper parallel port
(WPP)
Wrapper parallel
port
Wrapper serial
port
Standard port for
connection
Serial wrapper
control
Functional
outputs
Functional inputs
Functional
outputs
Functional inputs
Testing activators
CORE
CORE
Fig. 7.10 Structure of the IEEE 1500 standard: transit terminals of the core wrapper (a); mandatory
wrapper components (b) [68]
testing language (CTL) [65] used to described information about the tested core.
In order to satisfy requirements of the standard, each IP core in SoC shall have its
test wrapper. The wrapper is usually one cell of the so-called boundary register for
each functional I/O port, where all cells of this boundary register are called a wrapper
boundary register (WBR). It also comprises a wrapper instruction register (WIR) and
a wrapper bypass register (WBR). Figure 7.10 shows the structure of the high-level
core wrapper interface and mandatory components of the core wrapper.
By configuring functional WIR cores in SoC, it is possible to connect all WBR in
series by various means in order to ensure four main modes of SoC operation: normal
inward mode for core inspection, outward mode for interconnection inspection, and
bypass mode.
Test access to the cores embedded in SoC is ensured by core wrapper and the
so-called test access mechanism (TAM) embedded in the microcircuit. Figure 7.10a
shows two methods of accessing cores: mandatory access is provided through the
Wrapper Serial Ports (WSP), and additional access is provided through Wrapper
Parallel Ports (WPP). WSP provides a single-bit port for test data (WSI/WSO) with
test clocking (WRCK) and control signals (WSC), while WPP has a higher capacity
to ensure more effective implementation of tests.
It should be noted that the IEEE Std. 1500 does not involve using the WPP port;
therefore, the core provider is responsibe for designing this port. Due to this reason,
IIPS in the cited work [33] was designed using WSP exclusively. Here we also do
not discuss various architecture variants of a parallel TAM. If a certain structure
of parallel TAM is presented, scaling of the security test from the core level to the
SoC level can follow the same methodology as scaling of a traditional core test with
access to parallel testing.