7.3 Using the IEEE Std. 1500 Standard in Order …
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in the chip area are insignificant and even further reduced in case of shared use of
the same infrastructure by many other main security elements.
7.3.2 Introduction to IP Infrastructures
The so-called IP infrastructures (IIP) are sets of specialized IP blocks aimed at
ensuring high-quality functional safety inspection of an SoC. For example, Synopsys
Inc provides a set of various IPs for verification, which can be installed by the developer in SoC to verify certain bus protocols [58]. Most of these IP blocks are used by
responsible developers of SoC interface only during design phase and don’t physically exist in the created SoC. There are also IIPs that are actually modules built into a
microcircuit and specially designed to facilitate performance of post-production tests,
mitigate developer’s mistakes or improve technical and economical characteristics
of the microcircuit (percentage yield, temperature range, etc.). Structures suggested
in [56] can be cited as examples used in SoC tests: to estimate frequency parameters [59], eliminate the random error [60] and improve characteristics of digital
and analog mixed signals [61]. Moreover, certain companies provide such products
to test IP in order to improve the possibilities of checking microcircuits included
in boards [58]. The increased demand for special infrastructure logic embedded in
microcircuits for modernization of the testing process is due to the observed increase
in the frequency of occurrence of mistakes and random errors in modern SoC with
direct scaling of microcircuit designs for which standard external testing equipment
does not provide proper coverage or significantly increases testing time and costs
[62]. The IP infrastructure suggested in [33] has the same source design principles
as IIP for identification of Trojans or project errors in SoC. Nevertheless, its main
purpose is to increase SoC security and reliability.
7.3.3 IEEE 1500 Standard
Architecture of most modern SoC limits the possibility of external control and monitoring of internal functional blocks. In order to ensure effective checking of all main
IP cores at the microcircuit level, it is necessary to include special infrastructure
logic in the SoC hardware during the design stage. On the other hand, repeated
testing becomes an integral part of reusing IP in SoC development [63]. This calls
for the creation of standard protocol of such testing associated with testing methodology software that would allow testing different IP cores in a single test environment
and provide the possibility of scaling the sets of tests on all core levels created by
the core developer to the SoC level. IEEE Std. 1500 serves as such standard and is
specially developed for testing.
The IEEE Std. 1500 [64] standard contains two parts: (1) architecture of the test
core wrapper, which is necessary to organize access to embedded cores, and (2) core
669
in the chip area are insignificant and even further reduced in case of shared use of
the same infrastructure by many other main security elements.
7.3.2 Introduction to IP Infrastructures
The so-called IP infrastructures (IIP) are sets of specialized IP blocks aimed at
ensuring high-quality functional safety inspection of an SoC. For example, Synopsys
Inc provides a set of various IPs for verification, which can be installed by the developer in SoC to verify certain bus protocols [58]. Most of these IP blocks are used by
responsible developers of SoC interface only during design phase and don’t physically exist in the created SoC. There are also IIPs that are actually modules built into a
microcircuit and specially designed to facilitate performance of post-production tests,
mitigate developer’s mistakes or improve technical and economical characteristics
of the microcircuit (percentage yield, temperature range, etc.). Structures suggested
in [56] can be cited as examples used in SoC tests: to estimate frequency parameters [59], eliminate the random error [60] and improve characteristics of digital
and analog mixed signals [61]. Moreover, certain companies provide such products
to test IP in order to improve the possibilities of checking microcircuits included
in boards [58]. The increased demand for special infrastructure logic embedded in
microcircuits for modernization of the testing process is due to the observed increase
in the frequency of occurrence of mistakes and random errors in modern SoC with
direct scaling of microcircuit designs for which standard external testing equipment
does not provide proper coverage or significantly increases testing time and costs
[62]. The IP infrastructure suggested in [33] has the same source design principles
as IIP for identification of Trojans or project errors in SoC. Nevertheless, its main
purpose is to increase SoC security and reliability.
7.3.3 IEEE 1500 Standard
Architecture of most modern SoC limits the possibility of external control and monitoring of internal functional blocks. In order to ensure effective checking of all main
IP cores at the microcircuit level, it is necessary to include special infrastructure
logic in the SoC hardware during the design stage. On the other hand, repeated
testing becomes an integral part of reusing IP in SoC development [63]. This calls
for the creation of standard protocol of such testing associated with testing methodology software that would allow testing different IP cores in a single test environment
and provide the possibility of scaling the sets of tests on all core levels created by
the core developer to the SoC level. IEEE Std. 1500 serves as such standard and is
specially developed for testing.
The IEEE Std. 1500 [64] standard contains two parts: (1) architecture of the test
core wrapper, which is necessary to organize access to embedded cores, and (2) core