668
7 Countermeasures Against Hardware Trojans
Standard tested input
ports
Standard tested input
ports
Fig. 7.9 Secure IP infrastructure (IIPS)
methods of deliberately misleading hardware have been suggested for passive and
active protection of IP. As for large-scale cryptographic attacks, various countering
measures are known that require introducing the corresponding changes in the logic
level of the architecture or the electrical circuit.
There are also some safe scan architectures that can prevent attacks via scan
channels to a significant degree.
However, many of these security technologies require increasing the circuit area
and its power consumption may significantly reduce its performance. For example,
the solution in [52] increases the area and power consumption by the cryptographic
core by more than 200%, while the method [53] increases production costs by 38%.
The DfS circuit presented in [54] leads to a significant decrease in performance and
has certain scalability limitations. Of course, everyone would want to have an IP core
that is easy to implement and can be used as centralized security model for obtaining
end SoC structure with complex protection measures, low design, and labor costs. IP
infrastructures for SoC verification or checking are closest to such perfect solution
[55, 56], but this solution is aimed at ensuring complex protection against various
attacks.
Figure 7.9 shows the technical solution of specialized IP blocks with developed
infrastructure to ensure SoC security, which was named IIPS by the authors of [57].
Such IIPS module can effectively interact with other component cores in any SoC
by using the standard embedded core test (SECT) IEEE 1500. It can ensure complex
protection from various attacks by preventing them or facilitating the SoC security
validation process during production tests. This centralized module functions as a
self-sufficient core with the possibility to configure it for the SoC designer and can
be automatically interfaced with other standard cores in the SoC. Below we are going
to examine the general IIPS structure and the features of its interaction with other
cores. This module contains the so-called physical unclonable function (PUF), which
is also a basic function for verifying authenticity of the device; it can also be used to
generate a cryptographic key using a special structure embedded in the chip. Since
IIPS is outside the range of influence of other functional cores and activates only
during performance of tests or security provision tasks, there is no problem with
increasing power consumption in this case. For standard multi-core SoC, increases
7 Countermeasures Against Hardware Trojans
Standard tested input
ports
Standard tested input
ports
Fig. 7.9 Secure IP infrastructure (IIPS)
methods of deliberately misleading hardware have been suggested for passive and
active protection of IP. As for large-scale cryptographic attacks, various countering
measures are known that require introducing the corresponding changes in the logic
level of the architecture or the electrical circuit.
There are also some safe scan architectures that can prevent attacks via scan
channels to a significant degree.
However, many of these security technologies require increasing the circuit area
and its power consumption may significantly reduce its performance. For example,
the solution in [52] increases the area and power consumption by the cryptographic
core by more than 200%, while the method [53] increases production costs by 38%.
The DfS circuit presented in [54] leads to a significant decrease in performance and
has certain scalability limitations. Of course, everyone would want to have an IP core
that is easy to implement and can be used as centralized security model for obtaining
end SoC structure with complex protection measures, low design, and labor costs. IP
infrastructures for SoC verification or checking are closest to such perfect solution
[55, 56], but this solution is aimed at ensuring complex protection against various
attacks.
Figure 7.9 shows the technical solution of specialized IP blocks with developed
infrastructure to ensure SoC security, which was named IIPS by the authors of [57].
Such IIPS module can effectively interact with other component cores in any SoC
by using the standard embedded core test (SECT) IEEE 1500. It can ensure complex
protection from various attacks by preventing them or facilitating the SoC security
validation process during production tests. This centralized module functions as a
self-sufficient core with the possibility to configure it for the SoC designer and can
be automatically interfaced with other standard cores in the SoC. Below we are going
to examine the general IIPS structure and the features of its interaction with other
cores. This module contains the so-called physical unclonable function (PUF), which
is also a basic function for verifying authenticity of the device; it can also be used to
generate a cryptographic key using a special structure embedded in the chip. Since
IIPS is outside the range of influence of other functional cores and activates only
during performance of tests or security provision tasks, there is no problem with
increasing power consumption in this case. For standard multi-core SoC, increases