7.2 A Trojan-Resistant System …
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ones will experience problems due to disconnected (floating) inputs. This problem
is solved in secure SoC by using the Isol block that ensures connections of the
corresponding signal in a fixed sequence.
The work [1] contains examination of an original bus architecture, which is actually fault-resistant to certain types of attacks by hardware Trojans. Due to construction
of architecture of such original bus around the core using standard bus elements, such
as arbiter, address decoder, and bus matrix, such SoC architecture is fully compatible
with traditional systems. The authors considered effective mechanisms of identification of malicious attempts to block the bus, access the memory without authorization, and maliciously use waiting signals, which, if left undetected, can completely
stop operation of a one-chip system or cause significant disruptions to its operation. Depending on the specific nature of a Trojan attack, operation of such one-chip
system can be modified in the process, thus allowing this one-chip system to keep
preserving full or partial execution of its functions even regardless the performed
attack.
This experiment clearly deserves close attention of the specialists in the field of
designing safe systems on chips.
7.3 Using the IEEE Std. 1500 Standard in Order to Ensure
Safety of Systems on Chips
7.3.1 Introduction to the Problem
As noted above many times, with regard to various forms of possible methods of
unauthorized access to the SoC at the hardware level, all known methods of postproduction SoC testing cannot provide proper protection when used separately. We
examined these problems in the previous chapter.
In order to ensure effective protection from such threats, in order to develop
countermeasure, it is necessary to introduce special mechanisms for prevention of
such attacks or facilitation of their detection in case of an attack during the design
stage. The main threats detailed in [32–51] include the attacks initiated by hardware
Trojans in the form of various malicious changes in the design; theft of intellectual
property objects in hardware, such as illegal sale or change in IC IP cores; physical
attacks on cryptographic systems during Trojan activation, e.g., side-channel attacks,
failure-based attacks, and scan-based attacks. In order to prevent such attacks, the
researchers have suggested various methods, part of which has been considered above
in detail.
Let us recall that the researchers of this phenomenon suggested a number of
methods, e.g., the method of elimination of rare events and the use of the network
of ring oscillators for the purpose of detection of hardware Trojans or at least partial
prevention of their operation as safety engineering methods (DfS). Such methods
as physical unclonable function (PUF), special hardware changes in the IC and
667
ones will experience problems due to disconnected (floating) inputs. This problem
is solved in secure SoC by using the Isol block that ensures connections of the
corresponding signal in a fixed sequence.
The work [1] contains examination of an original bus architecture, which is actually fault-resistant to certain types of attacks by hardware Trojans. Due to construction
of architecture of such original bus around the core using standard bus elements, such
as arbiter, address decoder, and bus matrix, such SoC architecture is fully compatible
with traditional systems. The authors considered effective mechanisms of identification of malicious attempts to block the bus, access the memory without authorization, and maliciously use waiting signals, which, if left undetected, can completely
stop operation of a one-chip system or cause significant disruptions to its operation. Depending on the specific nature of a Trojan attack, operation of such one-chip
system can be modified in the process, thus allowing this one-chip system to keep
preserving full or partial execution of its functions even regardless the performed
attack.
This experiment clearly deserves close attention of the specialists in the field of
designing safe systems on chips.
7.3 Using the IEEE Std. 1500 Standard in Order to Ensure
Safety of Systems on Chips
7.3.1 Introduction to the Problem
As noted above many times, with regard to various forms of possible methods of
unauthorized access to the SoC at the hardware level, all known methods of postproduction SoC testing cannot provide proper protection when used separately. We
examined these problems in the previous chapter.
In order to ensure effective protection from such threats, in order to develop
countermeasure, it is necessary to introduce special mechanisms for prevention of
such attacks or facilitation of their detection in case of an attack during the design
stage. The main threats detailed in [32–51] include the attacks initiated by hardware
Trojans in the form of various malicious changes in the design; theft of intellectual
property objects in hardware, such as illegal sale or change in IC IP cores; physical
attacks on cryptographic systems during Trojan activation, e.g., side-channel attacks,
failure-based attacks, and scan-based attacks. In order to prevent such attacks, the
researchers have suggested various methods, part of which has been considered above
in detail.
Let us recall that the researchers of this phenomenon suggested a number of
methods, e.g., the method of elimination of rare events and the use of the network
of ring oscillators for the purpose of detection of hardware Trojans or at least partial
prevention of their operation as safety engineering methods (DfS). Such methods
as physical unclonable function (PUF), special hardware changes in the IC and