602
6 Reverse Engineering of Microcircuits
Fig. 6.72 IC cleavages decorated in Sirtl etchant: decoration time 3 s (a); decoration time 6 s (b);
decoration time 9 s (c)
This method is designed for preparation of sample chips of integrated microcircuits to be studied by electrophysical methods during sequential mechanical and
plasma-chemical removal of topology layers and is given in Appendix H.
6.7 Methods of Counteracting Microcircuit Re-engineering
Processes
6.7.1 Classification of the Main Methods of Counteracting
Microcircuit Re-engineering
As shown at the beginning of this chapter, the constantly increasing competition in the
global electronic component base (ECB) market has contributed to the active introduction of various reverse-engineering technologies that are used to reproduce chips
of individual products. On the other hand, a significant increase in the requirements
for ensuring information security of all recently created integrated circuits (ICs)
6 Reverse Engineering of Microcircuits
Fig. 6.72 IC cleavages decorated in Sirtl etchant: decoration time 3 s (a); decoration time 6 s (b);
decoration time 9 s (c)
This method is designed for preparation of sample chips of integrated microcircuits to be studied by electrophysical methods during sequential mechanical and
plasma-chemical removal of topology layers and is given in Appendix H.
6.7 Methods of Counteracting Microcircuit Re-engineering
Processes
6.7.1 Classification of the Main Methods of Counteracting
Microcircuit Re-engineering
As shown at the beginning of this chapter, the constantly increasing competition in the
global electronic component base (ECB) market has contributed to the active introduction of various reverse-engineering technologies that are used to reproduce chips
of individual products. On the other hand, a significant increase in the requirements
for ensuring information security of all recently created integrated circuits (ICs)