600
6 Reverse Engineering of Microcircuits
b)
c)
Fig. 6.70 Chemical decoration of the IC cleavage: without decoration (a); with decoration (b, c)
Figures 6.71, 6.72 and 6.73 show IC cleavages decorated in different etchants and
with different etching time
6.6.1.6 Methods for Preparing Samples to Be Examined Using SEM
These methods are designed to prepare samples of submicron ICs to study their
vertical topology on SEM using chemical decoration. The method sets out the procedure for preparation of an IC cleavage to be studied using SEM and is given in the
Appendix M.
6 Reverse Engineering of Microcircuits
b)
c)
Fig. 6.70 Chemical decoration of the IC cleavage: without decoration (a); with decoration (b, c)
Figures 6.71, 6.72 and 6.73 show IC cleavages decorated in different etchants and
with different etching time
6.6.1.6 Methods for Preparing Samples to Be Examined Using SEM
These methods are designed to prepare samples of submicron ICs to study their
vertical topology on SEM using chemical decoration. The method sets out the procedure for preparation of an IC cleavage to be studied using SEM and is given in the
Appendix M.