86
F. Firouzi et al.
Running Program
Interrupt
Pause & store state
Interrupt Service Routine (ISR)
Restore state & resume
Running Program
Handle and respond to interrupt
Fig. 2.27 How an interrupted is addressed in a processor by Interrupt Service Routine (ISR)
Vector tables and interrupt vectors are important to understanding both software
and hardware interrupts. Interrupt vectors are actual addresses that notify the
interrupt handler where the ISR can be found. For example, an ARM Cortex-M3
includes 255 interrupt vectors. Generally, a processor utilizes a vector table to hold
ISR addresses for each interrupt, and when an interrupt occurs, the processor obtains
the appropriate address from the vector table.
There are several processor architectures that facilitate nesting interrupts, meaning that when a low priority ISR is executed, a higher priority service is able to
preempt and suspend the ISR. The low priority ISR then resumes after the higher
priority ISR has resolved. The regulations governing a nested interrupt system
include [14]:
• Prioritization of all interrupts.
• An interrupt may occur at anytime, anywhere.
• If a higher priority ISR interrupts a lower priority ISR, the higher priority is
completed first.
• If a lower priority ISR interrupts a higher priority ISR, the higher priority finishes
execution prior to the execution of the lower priority.
• ISRs of equal priority level are executed in time order.
The NVIC (Nested Vector Interrupt Controller) found within the Cortex-M
family is an example of an interrupt controller that is highly flexible when it comes
to managing interrupt priorities. Nested Vector Interrupt Controllers allow several
interrupts to be defined and individual interrupts are given a priority, with “0”
recognized as the highest priority level. It is very important to remember that the
Cortex-M family utilizes a reverse numbering system for interrupts with higher
numbers indicating a lower priority value. It is also important to remember that
the priority level is programmable. The Cortex-M series offers several kinds of
interrupts (see Fig. 2.28) [8]:
• Interrupt Requests (IRQs) – Interrupts that are asynchronous and not connected
with the code currently in execution by the processor (i.e., ADC converter
completing conversion).
F. Firouzi et al.
Running Program
Interrupt
Pause & store state
Interrupt Service Routine (ISR)
Restore state & resume
Running Program
Handle and respond to interrupt
Fig. 2.27 How an interrupted is addressed in a processor by Interrupt Service Routine (ISR)
Vector tables and interrupt vectors are important to understanding both software
and hardware interrupts. Interrupt vectors are actual addresses that notify the
interrupt handler where the ISR can be found. For example, an ARM Cortex-M3
includes 255 interrupt vectors. Generally, a processor utilizes a vector table to hold
ISR addresses for each interrupt, and when an interrupt occurs, the processor obtains
the appropriate address from the vector table.
There are several processor architectures that facilitate nesting interrupts, meaning that when a low priority ISR is executed, a higher priority service is able to
preempt and suspend the ISR. The low priority ISR then resumes after the higher
priority ISR has resolved. The regulations governing a nested interrupt system
include [14]:
• Prioritization of all interrupts.
• An interrupt may occur at anytime, anywhere.
• If a higher priority ISR interrupts a lower priority ISR, the higher priority is
completed first.
• If a lower priority ISR interrupts a higher priority ISR, the higher priority finishes
execution prior to the execution of the lower priority.
• ISRs of equal priority level are executed in time order.
The NVIC (Nested Vector Interrupt Controller) found within the Cortex-M
family is an example of an interrupt controller that is highly flexible when it comes
to managing interrupt priorities. Nested Vector Interrupt Controllers allow several
interrupts to be defined and individual interrupts are given a priority, with “0”
recognized as the highest priority level. It is very important to remember that the
Cortex-M family utilizes a reverse numbering system for interrupts with higher
numbers indicating a lower priority value. It is also important to remember that
the priority level is programmable. The Cortex-M series offers several kinds of
interrupts (see Fig. 2.28) [8]:
• Interrupt Requests (IRQs) – Interrupts that are asynchronous and not connected
with the code currently in execution by the processor (i.e., ADC converter
completing conversion).