2 The Smart “Things” in IoT
85
CPU
Interrupt
from GPIO
Running Program
CPU
Interrupt Service Routine (ISR)
Poll GPIO
Poll GPIO
Poll GPIO
Polling-based System
Interrupt-based System
Interrupt Service Routine (ISR)
The state of GPIO changes at this point.
Therefore, CPU should respond
Fig. 2.26 How polling and interrupt work
stove. The timer acts like an interrupt and removing the eggs from the stove would
be the corresponding processing. When using the interrupt method, a state change
creates an interrupt signal telling the processor to pause a current operation and save
the present state before executing the processing connected to the interrupt. Then,
the previous state is restored and operations continue from the point of interruption.
Figure 2.26 compares the polling-based system with the interrupt-based system [13].
Interrupts can initiate from internal MCU devices or external devices. An
interrupt that originates from an external sensor or switch is often referred to as an
“attached interrupt,” because it is created by an external device connected to an IRQ
(interrupt request) pin in the MCU. When the appropriate status change is achieved,
an external device sends an IRQ to the pin. Next, the pin creates a notification
that is sent to the MCU’s interrupt controller. On the other hand, interrupts from
peripherals on the on-chip peripherals such as GPIO ports, internal times, etc. are
known as “peripheral interrupts.” These interrupts send a notification directly to an
interrupt controller without aid from the IRQ pin.
Interrupt controllers are responsible for moving IRQs to the CPU in a harmonious
manner. In the case of multiple interrupts, the controller must transmit them to the
CPU in the correct order, according to their respective priorities. The controller
must also perceive which interrupts are disabled (or masked) to disregard those
interrupts entirely. When the processor receives an IRQ from the controller, it
suspends its current program operations and saves all important information of the
processor, so that it can continue work after processing the interrupt. Next, the
processor loads and executes the associated processing program that matches the
IRQ received. This associated program is called ISR. An ISR (Interrupt Service
Routine, sometimes referred to as Interrupt Service Procedure) is a subroutine that
the processor executes to respond to a unique event/interrupt/exception. Once the
IRQ processing is finished, the CPU restores the saved work information and begins
working from the previous stopping point. The saving and the resuming process are
managed automatically by the processor (see Fig. 2.27) [13].
85
CPU
Interrupt
from GPIO
Running Program
CPU
Interrupt Service Routine (ISR)
Poll GPIO
Poll GPIO
Poll GPIO
Polling-based System
Interrupt-based System
Interrupt Service Routine (ISR)
The state of GPIO changes at this point.
Therefore, CPU should respond
Fig. 2.26 How polling and interrupt work
stove. The timer acts like an interrupt and removing the eggs from the stove would
be the corresponding processing. When using the interrupt method, a state change
creates an interrupt signal telling the processor to pause a current operation and save
the present state before executing the processing connected to the interrupt. Then,
the previous state is restored and operations continue from the point of interruption.
Figure 2.26 compares the polling-based system with the interrupt-based system [13].
Interrupts can initiate from internal MCU devices or external devices. An
interrupt that originates from an external sensor or switch is often referred to as an
“attached interrupt,” because it is created by an external device connected to an IRQ
(interrupt request) pin in the MCU. When the appropriate status change is achieved,
an external device sends an IRQ to the pin. Next, the pin creates a notification
that is sent to the MCU’s interrupt controller. On the other hand, interrupts from
peripherals on the on-chip peripherals such as GPIO ports, internal times, etc. are
known as “peripheral interrupts.” These interrupts send a notification directly to an
interrupt controller without aid from the IRQ pin.
Interrupt controllers are responsible for moving IRQs to the CPU in a harmonious
manner. In the case of multiple interrupts, the controller must transmit them to the
CPU in the correct order, according to their respective priorities. The controller
must also perceive which interrupts are disabled (or masked) to disregard those
interrupts entirely. When the processor receives an IRQ from the controller, it
suspends its current program operations and saves all important information of the
processor, so that it can continue work after processing the interrupt. Next, the
processor loads and executes the associated processing program that matches the
IRQ received. This associated program is called ISR. An ISR (Interrupt Service
Routine, sometimes referred to as Interrupt Service Procedure) is a subroutine that
the processor executes to respond to a unique event/interrupt/exception. Once the
IRQ processing is finished, the CPU restores the saved work information and begins
working from the previous stopping point. The saving and the resuming process are
managed automatically by the processor (see Fig. 2.27) [13].