2 The Smart “Things” in IoT
87
NVIC
Processor Core
NMI
SysTick IRQ
IRQs
System
Exception
Fig. 2.28 Nested Vector Interrupt Controller
• Non-maskable Interrupt (NMI) – Like IRQs, except that they cannot be disabled
(not maskable).
• SysTick Timer Input – SysTick is a timer with 24 bits counting from a preloaded
value to zero. When the counter transitions to zero, it can generate an interrupt.
• Exceptions, Faults, and Software Interrupts – These are synchronous and are
the result of executing a unique instruction (e.g., encountering an undefined
instruction or overflow due to the execution of a specific instruction).
2.5.6 Addressing Modes
Addressing modes are an integral part of instruction set architecture and define how
instructions can identify the operand of each instruction. The addressing mode rules
how an instruction address field is interpreted or modified before the instruction is
executed.
Immediate Addressing Also known as “literal addressing” uses the data in the
address field of instruction as an operand. In other words, the data is in the address
field of instruction.
Direct Addressing Mode Memory location’s address is directly given and specified in the instruction. This kind of instruction can only be utilized for special
function registers (SFR) or internal RAM (see Fig. 2.29).
Register Indirect Addressing Mode The memory location address is specified
indirectly in a register (see Fig. 2.30).
Register Relative Indirect Addressing Mode Effective memory location is calculated by adding the content of a register and an immediate value (see Fig. 2.31).
87
NVIC
Processor Core
NMI
SysTick IRQ
IRQs
System
Exception
Fig. 2.28 Nested Vector Interrupt Controller
• Non-maskable Interrupt (NMI) – Like IRQs, except that they cannot be disabled
(not maskable).
• SysTick Timer Input – SysTick is a timer with 24 bits counting from a preloaded
value to zero. When the counter transitions to zero, it can generate an interrupt.
• Exceptions, Faults, and Software Interrupts – These are synchronous and are
the result of executing a unique instruction (e.g., encountering an undefined
instruction or overflow due to the execution of a specific instruction).
2.5.6 Addressing Modes
Addressing modes are an integral part of instruction set architecture and define how
instructions can identify the operand of each instruction. The addressing mode rules
how an instruction address field is interpreted or modified before the instruction is
executed.
Immediate Addressing Also known as “literal addressing” uses the data in the
address field of instruction as an operand. In other words, the data is in the address
field of instruction.
Direct Addressing Mode Memory location’s address is directly given and specified in the instruction. This kind of instruction can only be utilized for special
function registers (SFR) or internal RAM (see Fig. 2.29).
Register Indirect Addressing Mode The memory location address is specified
indirectly in a register (see Fig. 2.30).
Register Relative Indirect Addressing Mode Effective memory location is calculated by adding the content of a register and an immediate value (see Fig. 2.31).