450
M. N. Bojnordi and P. Behnam
2R Cell
Network Parameters
Input Data
Multibit Sensor
Fig. 9.15 In situ XNOR operations for the MB-CNN convolution
adders (D) are set to 0 after computing each XNOR convolution. All of the C 0 and
C 1 flip-flops are configured by the chip controller based on the size of parameters
for the convolutional layers.
9.4.4.3 Array Structure
Each MB-CNN memory array is implemented using an RRAM crosspoint comprising M rows and N columns. Figure 9.15 shows an example 3 × 4 MB-CNN data
array. The RRAM cells are programmed to represent the binary network parameters
(i.e., filter weights). To enable in situ XNOR convolution within the crosspoint
arrays, a set of latches are provided at the periphery of the array to store the input
data, which are applied to the array through horizontal wordlines. Each input bit
requires two wires for its true and complement values. Along the lines of prior
proposals on using multibit sensing mechanisms for analog computation [61, 62, 72,
100], a cost-efficient multibit sensor circuit is employed for quantizing the bitline
voltage (sum). The proposed sensing circuit comprises a differential amplifier, a
sample and hold unit [101], and a digital-to-analog converter [102]. Due to the
exponential increase in the complexity of the sensor circuit with the number of
output bits, its precision is limited to 5 bits only. As a result, each array can compute
the sum of 32 partial XNOR convolutions.
9.4.4.4 Data Organization
One of the key challenges in performing an efficient MB-CNN convolution is how to
lay out data within and across memory arrays. This section describes how the inputs
and network parameters are mapped onto the MB-CNN accelerator. Figure 9.16
shows an illustrative example of the data organization MB-CNN. The size of feature
map the ith convolution layer is I c × h × w = 32 × 7 × 7, where c denotes the input
depth and h and w are the height and width, respectively. The input is convolved
with a kernel (K
c×h×w
0
= 32 × 2 × 2). Assuming that there are 128 such kernels,
M. N. Bojnordi and P. Behnam
2R Cell
Network Parameters
Input Data
Multibit Sensor
Fig. 9.15 In situ XNOR operations for the MB-CNN convolution
adders (D) are set to 0 after computing each XNOR convolution. All of the C 0 and
C 1 flip-flops are configured by the chip controller based on the size of parameters
for the convolutional layers.
9.4.4.3 Array Structure
Each MB-CNN memory array is implemented using an RRAM crosspoint comprising M rows and N columns. Figure 9.15 shows an example 3 × 4 MB-CNN data
array. The RRAM cells are programmed to represent the binary network parameters
(i.e., filter weights). To enable in situ XNOR convolution within the crosspoint
arrays, a set of latches are provided at the periphery of the array to store the input
data, which are applied to the array through horizontal wordlines. Each input bit
requires two wires for its true and complement values. Along the lines of prior
proposals on using multibit sensing mechanisms for analog computation [61, 62, 72,
100], a cost-efficient multibit sensor circuit is employed for quantizing the bitline
voltage (sum). The proposed sensing circuit comprises a differential amplifier, a
sample and hold unit [101], and a digital-to-analog converter [102]. Due to the
exponential increase in the complexity of the sensor circuit with the number of
output bits, its precision is limited to 5 bits only. As a result, each array can compute
the sum of 32 partial XNOR convolutions.
9.4.4.4 Data Organization
One of the key challenges in performing an efficient MB-CNN convolution is how to
lay out data within and across memory arrays. This section describes how the inputs
and network parameters are mapped onto the MB-CNN accelerator. Figure 9.16
shows an illustrative example of the data organization MB-CNN. The size of feature
map the ith convolution layer is I c × h × w = 32 × 7 × 7, where c denotes the input
depth and h and w are the height and width, respectively. The input is convolved
with a kernel (K
c×h×w
0
= 32 × 2 × 2). Assuming that there are 128 such kernels,