9 Emerging Hardware Technologies for IoT Data Processing
447
...
Shared Bitline
w 0 b 0
w 0
b 0
b 0
w 0
w 1 b 1
w 1
b 1
b 1
w 1
w n b n
w n
b n
b n
w n
(a) Multiple cells sharing a bitline
sum = Vdd
mH + (n-m)L
n(H + L)
Vdd
sum
L/m
Gnd
H/m
H/(n-m)
L/(n-m)
(b) Equivalent circuit
Fig. 9.11 Analog bit-count computation within the 2R crosspoint array. (a) Multiple cells sharing
a bitline. (b) Equivalent circuit
Fig. 9.12 The bitline voltage
versus the 1s in XNOR
outputs
sum
m
n
n/2
Vdd/2
four resistors. For a bitline connected to n 2R cells, assume that m XNOR operations
produce 1s in their outputs. (Notice that the binary outcome of an XNOR is high (1)
only if Vdd is connected to the RRAM cell with low resistance; otherwise, a low
voltage (0) appears at the output.) The resultant bitline voltage can then be computed
through sum = V dd
mH +(n−m)L
n(H +L) , where H and L are the amount of high and low
resistances of the RRAM cells. The bitline voltage is linearly proportional to the
number of 1s produced by the XNOR operations—i.e., the bit-count.
By quantizing the bitline voltage, the final binary value for a single convolution
can be computed. Figure 9.12 shows a linear relationship between the bitline voltage
and the number of cells that produce a 1 at the output. MB-CNN employs a
comparator that compares the sum against Vdd/2, thereby quantizing the final output
to 1 if sum ≥
V dd
2 and 0 otherwise.
9.4.3.2 In Situ Bit-Counting
MB-CNN employs an in situ bit-counting technique that requires having all the
operands connected to a single bitline during the XNOR convolution. Therefore,
large crosspoint arrays may be required to compute the bit-count of modern deep
learning workloads. Regrettably, such monolithic data arrays are largely impractical
due to significant limitations in sensing mechanisms, excessive power dissipation,
unacceptable latency of operations, and serious reliability problems. To address all
these challenges, MB-CNN employs a novel hierarchical mechanism for computing
partial bit-counts across multiple arrays. The partial counts are then aggregated into
a single value and then quantized into a single bit. The hierarchical mechanism
447
...
Shared Bitline
w 0 b 0
w 0
b 0
b 0
w 0
w 1 b 1
w 1
b 1
b 1
w 1
w n b n
w n
b n
b n
w n
(a) Multiple cells sharing a bitline
sum = Vdd
mH + (n-m)L
n(H + L)
Vdd
sum
L/m
Gnd
H/m
H/(n-m)
L/(n-m)
(b) Equivalent circuit
Fig. 9.11 Analog bit-count computation within the 2R crosspoint array. (a) Multiple cells sharing
a bitline. (b) Equivalent circuit
Fig. 9.12 The bitline voltage
versus the 1s in XNOR
outputs
sum
m
n
n/2
Vdd/2
four resistors. For a bitline connected to n 2R cells, assume that m XNOR operations
produce 1s in their outputs. (Notice that the binary outcome of an XNOR is high (1)
only if Vdd is connected to the RRAM cell with low resistance; otherwise, a low
voltage (0) appears at the output.) The resultant bitline voltage can then be computed
through sum = V dd
mH +(n−m)L
n(H +L) , where H and L are the amount of high and low
resistances of the RRAM cells. The bitline voltage is linearly proportional to the
number of 1s produced by the XNOR operations—i.e., the bit-count.
By quantizing the bitline voltage, the final binary value for a single convolution
can be computed. Figure 9.12 shows a linear relationship between the bitline voltage
and the number of cells that produce a 1 at the output. MB-CNN employs a
comparator that compares the sum against Vdd/2, thereby quantizing the final output
to 1 if sum ≥
V dd
2 and 0 otherwise.
9.4.3.2 In Situ Bit-Counting
MB-CNN employs an in situ bit-counting technique that requires having all the
operands connected to a single bitline during the XNOR convolution. Therefore,
large crosspoint arrays may be required to compute the bit-count of modern deep
learning workloads. Regrettably, such monolithic data arrays are largely impractical
due to significant limitations in sensing mechanisms, excessive power dissipation,
unacceptable latency of operations, and serious reliability problems. To address all
these challenges, MB-CNN employs a novel hierarchical mechanism for computing
partial bit-counts across multiple arrays. The partial counts are then aggregated into
a single value and then quantized into a single bit. The hierarchical mechanism