436
M. N. Bojnordi and P. Behnam
Graphics
Processor
DRAM
Module
500x
10x 1x
Fig. 9.2 The relative energy cost of computation and data movement between DRAM and GPU
fabrication complexities for the commodity computing systems while still relying
on the conventional memory architectures.
9.1.3 Bandwidth Limitation for Big Data Processing
Historically, the microprocessor core counts and the DRAM capacity have doubled
almost in every 2–3 years [14], which translates to a significantly higher rate than the
one experienced for bandwidth improvements. As a result, most computing systems
started to experience the bandwidth wall problem, where the off-chip bandwidth
has become a bottleneck for both performance and throughput. The demand for
memory bandwidth has been growing as the utilization of on-chip computational
units increases through out-of-order execution, multithreading, task pipelining, and
hardware specialization for data-intensive applications [15]. Moreover, to hide
the memory access latency in microprocessors, various forms of data prefetching
[16, 17] have been used that necessitate consuming more memory bandwidth.
Conventional interfacing technologies and the limited number of input/output pins
in the integrated circuit packages constrain the off-chip bandwidth significantly.
Recent achievements in high-speed serial links [18] and through-silicon vias (TSVs)
[19] can alleviate the issues by increasing the aggregate memory bandwidth at the
cost of introducing a new set of reliability issues and fabrication complexity.
9.2 Recent Innovations for Bandwidth and Energy
This section provides a brief overview of a few state-of-the-art solutions for the
energy-efficiency and bandwidth problems in the contemporary computing systems.
9.2.1 Heterogeneous Computing
Hardware accelerators have proven successful in achieving significant energyefficiency and speedup over the general-purpose processors mainly due to better
utilizing the computational and memory resources [20]. Along these lines, heteroge-
M. N. Bojnordi and P. Behnam
Graphics
Processor
DRAM
Module
500x
10x 1x
Fig. 9.2 The relative energy cost of computation and data movement between DRAM and GPU
fabrication complexities for the commodity computing systems while still relying
on the conventional memory architectures.
9.1.3 Bandwidth Limitation for Big Data Processing
Historically, the microprocessor core counts and the DRAM capacity have doubled
almost in every 2–3 years [14], which translates to a significantly higher rate than the
one experienced for bandwidth improvements. As a result, most computing systems
started to experience the bandwidth wall problem, where the off-chip bandwidth
has become a bottleneck for both performance and throughput. The demand for
memory bandwidth has been growing as the utilization of on-chip computational
units increases through out-of-order execution, multithreading, task pipelining, and
hardware specialization for data-intensive applications [15]. Moreover, to hide
the memory access latency in microprocessors, various forms of data prefetching
[16, 17] have been used that necessitate consuming more memory bandwidth.
Conventional interfacing technologies and the limited number of input/output pins
in the integrated circuit packages constrain the off-chip bandwidth significantly.
Recent achievements in high-speed serial links [18] and through-silicon vias (TSVs)
[19] can alleviate the issues by increasing the aggregate memory bandwidth at the
cost of introducing a new set of reliability issues and fabrication complexity.
9.2 Recent Innovations for Bandwidth and Energy
This section provides a brief overview of a few state-of-the-art solutions for the
energy-efficiency and bandwidth problems in the contemporary computing systems.
9.2.1 Heterogeneous Computing
Hardware accelerators have proven successful in achieving significant energyefficiency and speedup over the general-purpose processors mainly due to better
utilizing the computational and memory resources [20]. Along these lines, heteroge-