84
R. Dutta and N. Paitya
4 Conclusion
In summary, a TFET design is proposed which has the potential of high-power
THz applications. We have conducted a thorough analysis on the high-frequency
performance of SG-PI-TFET based on InN with suitable simulation results for the
first time with systematical studies and analyses of the device performance for future
development of other InN devices.
References
1. T. Nirschl, S. Henzler, J. Fischer et al., Scaling properties of the tunneling field effect transistor
(TFET): device and circuit. Solid State Electron. 50(1), 44–51 (2006)
2. Q. Zhang, W. Zhao, A. Seabaugh, Low-subthreshold-swing tunnel transistors. IEEE Electron
Device Lett. 27(4), 297–300 (2006)
3. W.Y. Choi, B.G. Park, J.D. Lee, Tunneling field effect transistor (TFET) with subthreshold
swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)
4. A.S. Verhulst, D. Leonelli, R. Rooyackers, G. Groeseneke, Drain voltage dependent analytical
model of tunnel field-effect transistors. J. Appl. Phys. 110(2), 024510 (2011)
5. S. Brocard, M. Pala, D. Esseni, Design options for heterojunction tunnel FETs with high on
current and steep sub-VT slope, in Proceedings of IEEE International Electron Devices Meeting
(IEDM), (San Francisco, CA, USA, 2012), pp. 1, 4, 5
6. W. Lee, W.Y. Choi, Influence of inversion layer on tunneling field-effect transistors. IEEE
Electron Device Lett. 32(9), 1191–1193 (2011)
7. K.T. Tsen, C. Poweleit, D.K. Ferry, H. Lu, W.J. Schaff, Observation of large electron drift
velocities in InN by ultrafast Raman spectroscopy. Appl. Phys. Lett. 86(22), 222103 (2005)
8. S.K. O’Leary, B.E. Foutz, M.S. Shur, L.F. Eastman, Potential performance of indium-nitridebased devices. Appl. Phys. Lett. 88(15), 152113 (2006)
9. C. Shen, S.-L. Ong, C.-H. Heng, G. Samudra, Y.-C. Yeo, A variational approach to the twodimensional nonlinear poisson’s equation for the modeling of tunneling transistors. IEEE
Electron Device Lett. 29, 1252–1255 (2008)
10. P. Wisniewski, B. Majkusiak, Modeling the tunnel field-effect transistor based on different
tunneling path approaches. IEEE Trans. Electron Devices 65(6), 2626–2631 (2018)
11. E.O. Kane, Theory of tunneling. J. Appl. Phys. 32(1), 83–91 (1961)
12. M.G. Bardon, H.P. Neves, R. Puers, C. Van Hoof, Pseudo two-dimensional model for doublegate tunnel FETs considering the junctions depletion regions. IEEE Trans. Electron Devices
57(4), 827–834 (2010)
13. E.O. Kane, Zener tunneling in semiconductors. J. Appl. Phys. Chem. Solids 12(2), 181–188
(1960)
14. Y. Khatami, K. Banerjee, Steep subthreshold slope n and p-type tunnel-FET devices for lowpower and energy efficient digital circuits. IEEE Trans. Electron Devices 56(11), 2752–2761
(2009)
15. S. Cho, J.S. Lee, K.R. Kim, B.G. Park, J.S. Harris, I.M. Kang, Analyses on small—signal
parameters and radio-frequency modeling of gate-all-around tunneling field effect transistors.
IEEE Trans. Electron Devices 58(12), 4164–4171 (2011)
16. J. Madan, R. Chaujar, Numerical simulation of N+ source pocket PIN-GAA-tunnel FET: impact
of interface trap charges and temperature. IEEE Trans. Electron Devices 64(4), 1482–1488
(2017)
R. Dutta and N. Paitya
4 Conclusion
In summary, a TFET design is proposed which has the potential of high-power
THz applications. We have conducted a thorough analysis on the high-frequency
performance of SG-PI-TFET based on InN with suitable simulation results for the
first time with systematical studies and analyses of the device performance for future
development of other InN devices.
References
1. T. Nirschl, S. Henzler, J. Fischer et al., Scaling properties of the tunneling field effect transistor
(TFET): device and circuit. Solid State Electron. 50(1), 44–51 (2006)
2. Q. Zhang, W. Zhao, A. Seabaugh, Low-subthreshold-swing tunnel transistors. IEEE Electron
Device Lett. 27(4), 297–300 (2006)
3. W.Y. Choi, B.G. Park, J.D. Lee, Tunneling field effect transistor (TFET) with subthreshold
swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)
4. A.S. Verhulst, D. Leonelli, R. Rooyackers, G. Groeseneke, Drain voltage dependent analytical
model of tunnel field-effect transistors. J. Appl. Phys. 110(2), 024510 (2011)
5. S. Brocard, M. Pala, D. Esseni, Design options for heterojunction tunnel FETs with high on
current and steep sub-VT slope, in Proceedings of IEEE International Electron Devices Meeting
(IEDM), (San Francisco, CA, USA, 2012), pp. 1, 4, 5
6. W. Lee, W.Y. Choi, Influence of inversion layer on tunneling field-effect transistors. IEEE
Electron Device Lett. 32(9), 1191–1193 (2011)
7. K.T. Tsen, C. Poweleit, D.K. Ferry, H. Lu, W.J. Schaff, Observation of large electron drift
velocities in InN by ultrafast Raman spectroscopy. Appl. Phys. Lett. 86(22), 222103 (2005)
8. S.K. O’Leary, B.E. Foutz, M.S. Shur, L.F. Eastman, Potential performance of indium-nitridebased devices. Appl. Phys. Lett. 88(15), 152113 (2006)
9. C. Shen, S.-L. Ong, C.-H. Heng, G. Samudra, Y.-C. Yeo, A variational approach to the twodimensional nonlinear poisson’s equation for the modeling of tunneling transistors. IEEE
Electron Device Lett. 29, 1252–1255 (2008)
10. P. Wisniewski, B. Majkusiak, Modeling the tunnel field-effect transistor based on different
tunneling path approaches. IEEE Trans. Electron Devices 65(6), 2626–2631 (2018)
11. E.O. Kane, Theory of tunneling. J. Appl. Phys. 32(1), 83–91 (1961)
12. M.G. Bardon, H.P. Neves, R. Puers, C. Van Hoof, Pseudo two-dimensional model for doublegate tunnel FETs considering the junctions depletion regions. IEEE Trans. Electron Devices
57(4), 827–834 (2010)
13. E.O. Kane, Zener tunneling in semiconductors. J. Appl. Phys. Chem. Solids 12(2), 181–188
(1960)
14. Y. Khatami, K. Banerjee, Steep subthreshold slope n and p-type tunnel-FET devices for lowpower and energy efficient digital circuits. IEEE Trans. Electron Devices 56(11), 2752–2761
(2009)
15. S. Cho, J.S. Lee, K.R. Kim, B.G. Park, J.S. Harris, I.M. Kang, Analyses on small—signal
parameters and radio-frequency modeling of gate-all-around tunneling field effect transistors.
IEEE Trans. Electron Devices 58(12), 4164–4171 (2011)
16. J. Madan, R. Chaujar, Numerical simulation of N+ source pocket PIN-GAA-tunnel FET: impact
of interface trap charges and temperature. IEEE Trans. Electron Devices 64(4), 1482–1488
(2017)