11 Hardware Realization of Arithmetic Operations
257
19
53
113
241
461
977
2011 4051
0
0.5
1
·10
5
1.07 · 10
5
83,799 85,116 84,895
90,821 92,106
25,946 27,655
0
4,047
4,078
3,183
4,179
5,931
6,509
7,581
7,168
0
Moduli
Area, cells
Area (in cells) comparison of our approach vs. Synopsys for 400-bit inputs
Synopsys Approach
19
53
113
241
461
977
2011 4051
0
0.5
1
·10
5
1.14 · 10
5
1.39 · 10
5
1.23 · 10
5
1.38 · 10
5
1.09 · 10
5
1.2 · 10
5
32,154 35,370
0
3,828
5,655
4,077
4,015
7,804
7,665
8,931
7,926
0
Moduli
Area, cells
Area (in cells) comparison of our approach vs. Synopsys for 500-bit inputs
Synopsys Approach
Topics of further research include:
1. Comparing different forms of representations (SOPs, Reed–Muller expansions,
binary decision diagrams) in the realization of partial products;
2. Designing FPGAs using Xilinx and Altera architectures.
References
1. Bibilo, P., Cheremisinova, L., Kardash, S., Kirienko, N., Romanov, V., Cheremisinov, D.:
Automatizations of the logic synthesis of CMOS circuits with low power consumption.
Programnaia Ingeniria 8, 35–41 (2013) (in Russian)