256
D. Gorodecky and T. Villa
19
53
113
241
461
977
2011 4051
0
1
2
3
·10
4
19,886
26,196 26,708
28,923
26,559
30,242
16,445
18,261
0
2,124
2,259
1,895
2,193
2,983
3,859
4,045
3,891
0
Moduli
Area, cells
Area (in cells) comparison of our approach vs. Synopsys for 200-bit inputs
Synopsys Approach
19
53
113
241
461
977
2011 4051
0
2
4
6
·10
4
65,686
58,825
52,218 50,863
60,610 60,237
24,794 26,643
0
2,854
3,648
2,772
2,823
4,526
5,547
5,735
5,214
0
Moduli
Area, cells
Area (in cells) comparison of our approach vs. Synopsys for 300-bit inputs
Synopsys Approach
11.7 Conclusions and Further Research
Performance of computer arithmetic is one of the main advantages of RNS vs.
traditional approaches. We proposed a technique that improves significantly area
and performance of RNS vs. synthesis using standard EDA tools.
The experiments show significant gains by our approach vs. Synopsys. The gain
in performance is up to 30 times and in area is up to 15 times. Moreover, Synopsys
could not synthesize circuits for inputs X larger than 500 bits: the synthesis by
Synopsys of the modulo function for a 600-bit input X failed after 9 days, whereas
it takes only 20 min with our approach.
Our approach is not limited to modular multiplication and to the modulo function,
but it can be extended to any arithmetic operation. Dozens of circuits were designed
with the technique presented here and then embedded in arithmetic units by the
hi-tech factory integral (Minsk, Belarus).