Thus, complex instructions of most processors for embedded systems are
implemented by a sequence of simple instructions. For embedded systems, there is
therefore developed set of performance evaluation, so-called embedded
benchmarks.
17.5.6 Embedded Benchmarks
Benchmarks for embedded computing systems vary accordingly applications due to
RT, HRT, PW, and CW performance requirements where RT stands for real time,
HRT means hard real time, PW is power-wise and CW is cost-wise performance
requirements, respectively.
That is why material presented above is important. There is one a bit more
known benchmark developed by Embedded Microprocessor Benchmark
Consortium (EEMBC). It has five categories: automotive/industrial, consumer,
networking, office automation, and telecommunications.
Selecting Table 17.5 what this benchmark is (taken from Hennessy book recommended earlier), full site consists of 34 kernels in five classes.
Table 17.4 Comparative performance of MIPs and ReP
Processor and instruction mix
Ratio
MIPs 26%* 2L+19%*1L+12*1L +10*2L +9*1L +5*1L +4*1L +6*1L +8*1L
¼1.67
ReP 26%* L +(19*1L +36L +10*2L +18*1L +6*1L)/2 +5*1L
Table 17.3 (continued)
MIPs instruction
ReP instructions
Integer average (%)
Instruction
Memory traffic
Instruction
Memory traffic
Load imm
1L
LOAD
2L/2
2
Shift
1L
SHIFT
1L/2
2
Cond move
1L
COMPARE
1L/2
1
XOR
1L/2
CBR
1L/2
MOVE
1L/2
Jump
1L
MV
1L/2
1
CBR
1L/2
Call
1L
MV
1L/2
1
CBR
1L/2
Return
1L
MV
1L/2
1
CBR
1L/2
Total
99
238
17 On Performance: From Hardware up to Distributed Systems