section all hardware links activated: for ALU, operand’s addresses and signs (such
as N, Z, V, C).
Preparation of operands means that input ports are activated and buffers for
instruction data are enabled. For big instructions, it means that instruction execution
will be postponed until all memory cycles required to upload operands in processor
are complete.
Execution of instruction assumes that ALU (or combination of them) are ready
and perform instruction from operation field (ADD, SUB, etc.) in assumption that
required operands are ready and delivered from memory (or registers) to internal
buffers.
Thus, performance of active zone might be estimated as
Perf AZ ¼
1
T AZ
ð17:5Þ
while
Taz = T loading + T decoding + T preparation of operands + T execution + T loading back
Pretty much the same one might do with passive and interfacing zones.
Let us have a look for illustrative purposes how instruction is executed by
recoverable processor (ReP) made by ITACS Ltd. and prototyped with partial
support by grant of FP6 www.onbass.org (Fig. 17.14).
At first from instruction register through control unit via control bus microinstruction goes to either AU or LU. At the same time, microinstruction about
!Instruction
Register
Control
Unit
Register
File
Rbuf(R*)
AU
3-state
3-state
MUX
MUX
Control Bus
Data Bus
Data out
Data in
Hardware for Error Detection (P1)
Hardware for Error Recovery (P2)
Hardware for Data Manipulation (P3)
Check
GNR
Check
Check
LU
Fig. 17.14 REP structure
234
17 On Performance: From Hardware up to Distributed Systems