operands of instruction goes to register file and chosen operands go via three-state
buffers down to either AU or LU. When all signals are arrived and timing diagram
cycle is competed, information processed and arrived at the last right three-state
buffer.
When confirmation from checking schemes arrives, i.e., no errors are detected,
the right three-state buffer will release information to deliver either back to register
file or through interfacing zone out of processor to the memory or bus.
The picture of prototype of ReP (Fig. 17.15) might be useful to analyze from the
performance point of view and organization of embedded system.
Clear visible active zone and passive zone as well as board traces define performance of ReP. Interesting bit of this design is limitation of instructions complexity; only simple instruction to get or put data from and to outside world, store
and read data from active zone, and process data inside active zone are allowed.
Thus, when we need fast calculation, processor is performing it with maximum
frequency, without waiting of memory of IZ. In turn, clear read/write instructions
limit slow down from interaction with external world.
Fig. 17.15 Prototype of ReP
17.5 Hardware Performance
235
buffers down to either AU or LU. When all signals are arrived and timing diagram
cycle is competed, information processed and arrived at the last right three-state
buffer.
When confirmation from checking schemes arrives, i.e., no errors are detected,
the right three-state buffer will release information to deliver either back to register
file or through interfacing zone out of processor to the memory or bus.
The picture of prototype of ReP (Fig. 17.15) might be useful to analyze from the
performance point of view and organization of embedded system.
Clear visible active zone and passive zone as well as board traces define performance of ReP. Interesting bit of this design is limitation of instructions complexity; only simple instruction to get or put data from and to outside world, store
and read data from active zone, and process data inside active zone are allowed.
Thus, when we need fast calculation, processor is performing it with maximum
frequency, without waiting of memory of IZ. In turn, clear read/write instructions
limit slow down from interaction with external world.
Fig. 17.15 Prototype of ReP
17.5 Hardware Performance
235