In turn, active zone might consist of (even within a mobile telephone) several
information processing units for parallel execution of tasks or specific sequence of
instructions such as data coding and signal processing. Detailed description of the
zones, and their involvement in instruction execution, therefore, might help to
estimate the performance of embedded device.
17.5.3 Performance Estimation—Instruction Timing
To do performance estimation of embedded and any other computer system, we
have to assume following points:
• Mix of instructions with weight of all types of instructions defining the system
performance.
• Time required to perform any instruction—it is worth to separate AZ, IZ, and PZ
when instruction is executed.
• Note that instructions that use IZ (external) part are not defined in completion
time.
Thus, a mixture of presented types of instructions with taken into account an
amount of each of them is a good reflection of overall hardware performance.
In other words, hardware performance might be calculated by summarized
length of the instructions required to process user task. Let us consider what is AZ
and others in terms of overheads:
T instruction execution ¼ Tz þ Tiz þ Tpz
ð17:4Þ
Obviously, the shorter the cycle of instruction, the better the instructions of A, B, C,
D, E, F, and G types that are preferable. It is possible to calculate what difference
one might face if use H, I, and K types of instructions, but it is clear that 10
−9 , 10
−5 ,
and 10
−6 do not fit together well.
It is worth to analyze active zone performance in terms of instruction execution
phases:
• Loading,
• Decoding an instruction,
• Preparation of operands,
• Execution of the instruction, and
• Loading back modified operand
Loading means that instruction from memory goes to the load register in parallel
with increment of program counter (inside processor) and goes through decoding
scheme that activates requires activation operands and execution device ALU.
Decoding means that instruction (loaded from memory) is placed in the internal
register (not always addressable) inside processor and by special timing diagram
17.5 Hardware Performance
233
information processing units for parallel execution of tasks or specific sequence of
instructions such as data coding and signal processing. Detailed description of the
zones, and their involvement in instruction execution, therefore, might help to
estimate the performance of embedded device.
17.5.3 Performance Estimation—Instruction Timing
To do performance estimation of embedded and any other computer system, we
have to assume following points:
• Mix of instructions with weight of all types of instructions defining the system
performance.
• Time required to perform any instruction—it is worth to separate AZ, IZ, and PZ
when instruction is executed.
• Note that instructions that use IZ (external) part are not defined in completion
time.
Thus, a mixture of presented types of instructions with taken into account an
amount of each of them is a good reflection of overall hardware performance.
In other words, hardware performance might be calculated by summarized
length of the instructions required to process user task. Let us consider what is AZ
and others in terms of overheads:
T instruction execution ¼ Tz þ Tiz þ Tpz
ð17:4Þ
Obviously, the shorter the cycle of instruction, the better the instructions of A, B, C,
D, E, F, and G types that are preferable. It is possible to calculate what difference
one might face if use H, I, and K types of instructions, but it is clear that 10
−9 , 10
−5 ,
and 10
−6 do not fit together well.
It is worth to analyze active zone performance in terms of instruction execution
phases:
• Loading,
• Decoding an instruction,
• Preparation of operands,
• Execution of the instruction, and
• Loading back modified operand
Loading means that instruction from memory goes to the load register in parallel
with increment of program counter (inside processor) and goes through decoding
scheme that activates requires activation operands and execution device ALU.
Decoding means that instruction (loaded from memory) is placed in the internal
register (not always addressable) inside processor and by special timing diagram
17.5 Hardware Performance
233