The resulting offset is called effective address and can constitute of either positive or negative values except for the scaling factor.
The ERRIC architecture provides only direct memory addressing which results
in longer code as the addresses must be explicitly computed before the data can be
loaded. Table 15.3 compares the offsets sizes that are directly encoded in the
instruction. If not mentioned differently, the offset is always relative to the current
instruction pointer.
The ERRIC architecture does not allow encoding the offset in an instruction but
must always be given as an absolute address in a register. Thus, it requires an
additional “load constant” instruction, which requires another 8 bytes
(Load + NOP + 4 Byte constant). In terms of code safety, absolute jumps are
preferable as calculated jumps (relative) are more susceptible to faults than absolute
jumps.
Table 15.4 compares the instructions required in each architecture to perform
basic RISC operations such as load, stores, etc. A sequence of instructions is given
Table 15.3 Offset size of encoded instructions
Offset size encoded in
instructions (in bits)
ERRIC x86
SPARC
v8
ARM ARM
thumb
Unconditional jump/call
0
8–32 signed, rel. or
absolute, direct or indirect
30
24
11
Conditional branch
0
8–32 signed
19
24
8
Table 15.4 Comparison of selected instructions
Instruction
ERRIC
x86
SPARC v8
ARM
ARM
thumb
Load word
LD
MOV
LD
LDR
LDR
Load byte
signed
–
MOVSX
LDSB
LDRSB LDRSB
Load byte
unsigned
LD,
LDA,
AND;
a
MOV
LDUB
LDRB
LDRB
Store word
ST
MOV
ST
STR
STR
Store byte
–
b
MOV
STB
STRB
STRB
Add
ADD
ADD
ADD
ADD
ADD
Add (trap if
overflow)
–
ADD, INTO
ADDcc, TVS
ADDS,
SWIVS
ADD,
BVC +4
SWI
Sub
SUB
SUB
SUB
SUB
SUB
Sub (trap if
overflow)
–
SUB, INTO
SUBcc, TVS
SUBS,
SWIVS
SUB,
BVC +4
SWI
Multiply
–
MUL; IMUL
MULX
MUL
MUL
Divide
–
DIV; IDIV
DIVX
–
–
(continued)
15.1 Processor Architecture Overview
211
The ERRIC architecture provides only direct memory addressing which results
in longer code as the addresses must be explicitly computed before the data can be
loaded. Table 15.3 compares the offsets sizes that are directly encoded in the
instruction. If not mentioned differently, the offset is always relative to the current
instruction pointer.
The ERRIC architecture does not allow encoding the offset in an instruction but
must always be given as an absolute address in a register. Thus, it requires an
additional “load constant” instruction, which requires another 8 bytes
(Load + NOP + 4 Byte constant). In terms of code safety, absolute jumps are
preferable as calculated jumps (relative) are more susceptible to faults than absolute
jumps.
Table 15.4 compares the instructions required in each architecture to perform
basic RISC operations such as load, stores, etc. A sequence of instructions is given
Table 15.3 Offset size of encoded instructions
Offset size encoded in
instructions (in bits)
ERRIC x86
SPARC
v8
ARM ARM
thumb
Unconditional jump/call
0
8–32 signed, rel. or
absolute, direct or indirect
30
24
11
Conditional branch
0
8–32 signed
19
24
8
Table 15.4 Comparison of selected instructions
Instruction
ERRIC
x86
SPARC v8
ARM
ARM
thumb
Load word
LD
MOV
LD
LDR
LDR
Load byte
signed
–
MOVSX
LDSB
LDRSB LDRSB
Load byte
unsigned
LD,
LDA,
AND;
a
MOV
LDUB
LDRB
LDRB
Store word
ST
MOV
ST
STR
STR
Store byte
–
b
MOV
STB
STRB
STRB
Add
ADD
ADD
ADD
ADD
ADD
Add (trap if
overflow)
–
ADD, INTO
ADDcc, TVS
ADDS,
SWIVS
ADD,
BVC +4
SWI
Sub
SUB
SUB
SUB
SUB
SUB
Sub (trap if
overflow)
–
SUB, INTO
SUBcc, TVS
SUBS,
SWIVS
SUB,
BVC +4
SWI
Multiply
–
MUL; IMUL
MULX
MUL
MUL
Divide
–
DIV; IDIV
DIVX
–
–
(continued)
15.1 Processor Architecture Overview
211