Compared to the ARM, the ERRIC has less than half the number of instructions,
making it much simpler. On the downside, more elaborate instructions must be
emulated such as relative memory accesses or procedure calls.
Especially, the latter is very efficiently implemented on the ARM by the “load
multiple” and “store multiple” instructions that allow to efficiently putting all
procedure arguments on the stack. ERRIC on the other hand has to store all
arguments individually on the stack.
Table 15.2 shows the various data addressing modes supported by the various
architectures.
Although some SPARC does not directly provide an absolute addressing mode,
the register + register mode with a nullified second register is used to emulate this.
The SPARC architecture even provides a register which is always nullified, thus the
absolute addressing does not incur any performance penalty.
The x86 addressing modes are more powerful than the RISC ones; thus, instead
of extending the above table, the x86 addressing modes are summarized in
Fig. 15.1.
The offset part of a memory address can be either a static displacement or
through an address computation made up of one or more elements in Fig. 15.1.
Table 15.2 Supported addressing modes
Data addressing mode
ERRIC x86 SPARC v8 ARM ARM thumb
Register
X
X
(X)
X
X
Register + offset (displacement or based) –
X
X
X
X
Register + register (indexed)
–
X
X
X
X
Register + scaled register (scaled)
–
X
–
X
–
Register + offset and update register
–
–
–
X
–
Register + register and update register
–
–
–
X
–
Fig. 15.1 x86 addressing modes
210
15 Architecture Comparison and Evaluation