The CPU architecture summary given in Table 15.1 clearly illustrates the simplicity of the ERRIC processor architecture with its 16 instructions, which is by a
large margin smaller than the other architectures.
However, the simplicity is not for free. It comes at the cost of less powerful
instructions in comparison to the other instruction sets and results thus in longer
code. With longer code, we mean that the number of instructions is higher, not
necessarily the code size, as the instructions are only 16-bit wide.
The load from memory serves as a typical example, where in case of array
accesses the absolute memory address must be explicitly calculated and stored in a
register prior to the memory access, where, for example, in the SPARC architecture
the offset to the base address can be stored in a distinct register and then added on
the fly in the load instruction itself. The ARM even allows encoding an offset to a
base address given in a register directly in the instruction itself.
The ARM Thumb instruction set is a subset of the standard 32-bit ARM instruction set. It is intended for resource-constraint environments, where only a
16-bit data bus is available and it increases the code density.
The Thumb mode does not change the ARM architecture at all; in specific, the
address space is still 32-bit and all registers are 32-bit wide. However, only registers
R0–R7 are directly accessible, and R8–R16 are hidden. The stack register (SR) and
the link register (LR) are accessed by some instructions.
Interestingly, exceptions (interrupts) always trigger a processor switch to the
32-bit ARM mode prior to executing the exception handler. This supports the
statement by Hennessy [4, 5] that the 16-bit mode is not supposed to be a full
architecture, but “they [the instructions] are enough to encode most procedures.”
In contrast to this, we say that the ERRIC instruction set, although it is even
more constraint than the Thumb instruction set, is intended to be used as a full
instruction set, generic enough to encode all language features.
Table 15.1 (continued)
ERRIC
x86
SPARC v8
ARM7TDMI
(ARMv5-TE)
ARM7TDMI
thumb
I/O
Memory
mapped
Instructions,
memory
mapped
Memory
mapped
Memory
mapped
Memory
mapped
Pipeline length No pipeline
Atom: 16 Core
i7/Core
2: 14
Pentium4: 20–
31
Leon 3: 7
SPARC64 V:
15
UltraSPARC
T2: 8
3
3
Specialities
Very simple
instructions,
built-in fault
tolerance
Instructions of
variable size,
grown
instruction set,
memory
operands
Register
window,
delayed
control
transfer
Conditional
instruction
execution
32-bit ARM
instructions
partly
required.
Solved with
Thumb 2
mode
15.1 Processor Architecture Overview
209
large margin smaller than the other architectures.
However, the simplicity is not for free. It comes at the cost of less powerful
instructions in comparison to the other instruction sets and results thus in longer
code. With longer code, we mean that the number of instructions is higher, not
necessarily the code size, as the instructions are only 16-bit wide.
The load from memory serves as a typical example, where in case of array
accesses the absolute memory address must be explicitly calculated and stored in a
register prior to the memory access, where, for example, in the SPARC architecture
the offset to the base address can be stored in a distinct register and then added on
the fly in the load instruction itself. The ARM even allows encoding an offset to a
base address given in a register directly in the instruction itself.
The ARM Thumb instruction set is a subset of the standard 32-bit ARM instruction set. It is intended for resource-constraint environments, where only a
16-bit data bus is available and it increases the code density.
The Thumb mode does not change the ARM architecture at all; in specific, the
address space is still 32-bit and all registers are 32-bit wide. However, only registers
R0–R7 are directly accessible, and R8–R16 are hidden. The stack register (SR) and
the link register (LR) are accessed by some instructions.
Interestingly, exceptions (interrupts) always trigger a processor switch to the
32-bit ARM mode prior to executing the exception handler. This supports the
statement by Hennessy [4, 5] that the 16-bit mode is not supposed to be a full
architecture, but “they [the instructions] are enough to encode most procedures.”
In contrast to this, we say that the ERRIC instruction set, although it is even
more constraint than the Thumb instruction set, is intended to be used as a full
instruction set, generic enough to encode all language features.
Table 15.1 (continued)
ERRIC
x86
SPARC v8
ARM7TDMI
(ARMv5-TE)
ARM7TDMI
thumb
I/O
Memory
mapped
Instructions,
memory
mapped
Memory
mapped
Memory
mapped
Memory
mapped
Pipeline length No pipeline
Atom: 16 Core
i7/Core
2: 14
Pentium4: 20–
31
Leon 3: 7
SPARC64 V:
15
UltraSPARC
T2: 8
3
3
Specialities
Very simple
instructions,
built-in fault
tolerance
Instructions of
variable size,
grown
instruction set,
memory
operands
Register
window,
delayed
control
transfer
Conditional
instruction
execution
32-bit ARM
instructions
partly
required.
Solved with
Thumb 2
mode
15.1 Processor Architecture Overview
209