15.1 Processor Architecture Overview
Table 15.1 gives an architectural overview of the mentioned architectures. The
overview and analysis are inspired and adapted from the architectural comparison in
[4]. All information to compile the table were acquired from various documents
[1, 4–9].
Table 15.1 Processor architecture comparison
ERRIC
x86
SPARC v8
ARM7TDMI
(ARMv5-TE)
ARM7TDMI
thumb
Date
announced
2006
1978
1987
1985
1995
Architecture
family
Reduced
RISC
CISC
RISC
RISC
RISC
Integer
registers
32 Â 32 bits 8 Â 32 bits
31 Â 32 bits
15 Â 32 bits
8 Â 32
bits + SR, LR
Floating-point
registers
0
Optional
8 Â 32 bits or
8 Â 64 bits
(8 Â 80 bits
internal)
32 Â 32 bits
or 16 Â 64
bits or
8 Â 128 bits
Optional
32 Â 32 bits
or 16 Â 64
bits
Optional
32 Â 32 bits
or 16 Â 64
bits
Vector registers 0
Optional
8 Â 64 bits or
8 Â 128 bits
0
Optional
32 Â 32 bits
or 16 Â 64
bits
0
Address space
32 bits, flat
32 bits, flat or
segmented
32 bits, flat
32 bits, flat
32 bits, flat
Instruction size
(bytes)
2
1 –15
4
4
2
Multiprocessor
capable
No
Yes
Yes
Yes
No
Processor
modes
1
3 operation
modes
2
7
7
Data aligned
Yes
No
Yes
Yes
Yes
Memory
management
unit
No
Yes
Optional
Optional
Optional
Memory
addressing
modes
1
7
2 (reg
ind + disp,
reg ind.
indexed)
6
6
Memory
addressing
sizes
32-bit
8, 16, 32 bit
8, 16, 32, 64
bit
8, 16, 32 bit
8, 16, 32 bit
Number of
instructions
16
138 Integer
and logic 92
floating-point
total: 332
72
53
37
(continued)
208
15 Architecture Comparison and Evaluation