if an instruction is not available in the instruction set. A “–” means that more than a
short instruction sequence is required to simulate the specific functionality, typically
a longer sequence of inline code or a library call. As the ERRIC architecture does
not include a floating-point unit, we omit here all floating-point instructions, as all
of them are emulated in software.
References
1. Schagaev et al (1989) Instruction set and their impact on modern computer architecture.
Zarubeznya Electronica, No 7:8 (In Russian)
2. LEON3-FT SPARC V8 - RTAX - Data Sheet and User’s manual. Aeroflex Gaisler AB,
Goeteborg, Sweden, 1.1.0.8 edition, June 2009
3. Verlag H (2009) ARM: Nachwuchs fr die die cortex-a-familie. World Wide Web electronic
publication, October 2009
Table 15.4 (continued)
Instruction
ERRIC
x86
SPARC v8
ARM
ARM
thumb
AND
AND
AND
AND
AND
AND
OR
OR
OR
OR
ORR
ORR
XOR
XOR
XOR
XOR
EOR
EOR
NOT
NOT
Shift logical
left
SLL
c
SHL
SLL
LSL
LSL
Shift logical
right
SLR
c
SHR
SRL
LSR
LSR
Shift
arithmetic
right
SAR
c
SAR
SRA
Compare
CND
CMP
SUBcc rO,
CMP
CMP
Conditional
branch
CBR
JG; JNLE; JGE; JNL; JL;
JNGE; JLE; JNG; JNO; JNS;
JO; JS
BR_Z, BPcc (<,
> ,
, ! , = ,
#)
B
B
Call
CBR
CALL
CALL
BL
BL
Trap
CBR
INT n
TIcc, SIR
SWI
SWI
Return from
interrupt
RETI
IRET
DONE; RETRY;
RETURN
MOVS
pc, rl4
–
d
NOP
NOP
NOP
SETHI r0, 0
MOV
r0, r0
MOV r0,
r0
a
If the 8-bit data is aligned, the sequence LD, LDA, and AND can be used; otherwise, an LD and an
appropriate number of shift operations must be used
b For storing an 8-bit value, the destination address must be loaded, the appropriate bits cleared using a bit
mask, the argument shifted, and then written back to memory. In other words, omit using 8-bit values
c
Only one bit
d Interrupt is always handled in 32-bit mode. Thus, a pure 16-bit Thumb CPU without 32-bit mode is not
supported
212
15 Architecture Comparison and Evaluation