The simplified architecture presented in Fig. 14.3 allows implementation of
GAFT at instruction level. As before the three processes are essential for the
guaranteed and successful execution of each instruction.
Two processes P1 and P2 (blue and red) cope with fault checking and recovering
of malfunctions, respectively.
Fig. 14.2 ERRIC instruction execution—extended version
200
14 Hardware: The ERRIC Architecture
GAFT at instruction level. As before the three processes are essential for the
guaranteed and successful execution of each instruction.
Two processes P1 and P2 (blue and red) cope with fault checking and recovering
of malfunctions, respectively.
Fig. 14.2 ERRIC instruction execution—extended version
200
14 Hardware: The ERRIC Architecture