However, complicated functions are best handled by the compiler instead of
having specialized instructions within the ISA dedicated to very particular tasks.
The program size of applications compiled for ERRIC is indeed often larger than
the same application compiled for other architectures.
The 16-bit instructions help to keep code size small, but the lack of direct
immediate support in instructions increases code size significantly. The lack of
some often used instructions, such as multiplications, also increases code size, as
the corresponding library calls need additional setup code. However, we consider
this as acceptable to keep the processor architecture simple.
The processor has a large register file with 32 32-bit wide general-purpose
registers. All normal instructions expect exactly two input registers and save the
result of the operation in the second register, therefore always overwriting the
second operand content. Memory access is only possible for 32 bit at a time and has
to be aligned.
The ERRIC processor has an internal state (F1, F2), which is required by the
special memory controller. The main philosophy of the ERRIC architecture is to
keep it simple, which is not only applied to the processor but also to the memory
controller. The processor and memory controller are designed not to stall the
processor due to pending memory operation.
This is achieved by interleaving instruction fetch and memory operations. All
ERRIC instructions are 16-bit wide; an instruction fetch operation therefore always
loads two instructions from memory and stores them in a processor internal
instruction register (IR).
In sequential instruction execution, the compiler can schedule memory
instructions in every second instruction slot where no instruction has to be loaded
by the processor. This concept is illustrated in Fig. 14.2, which shows an extended
version of Fig. 14.1 that includes memory operations.
In state F1, the processor fetches an instruction from memory, and the memory
unit is therefore busy in this cycle and cannot execute a memory operation at the
same time. If the processor is in state F2 (not in state F1), the processor can execute
a memory instruction. The compiler is responsible to schedule the instruction in
proper order.
If the executed instruction is a branch, the processor switches automatically to
the F1 state as the memory controller can only load 32-bit aligned addresses. Jump
destination locations must therefore also be 32-bit aligned. All these requirements
force the compiler to fill gaps with NOP operations.
The main structure of the processor architecture is shown in Fig. 14.3. The
instructions are fetched from memory into the instruction register and decoded by
the control unit, which also manages the execution of each instruction.
The operands for each executed instruction are fetched from either the register
file or memory, multiplexed into the Arithmetic and Logic Unit (ALU) for operation. The output data from the ALU go either to memory through the data bus or is
written back to the register file. The current value and type of the data might also
indicate an address for branch instructions.
14.1 Processor Architecture
199
having specialized instructions within the ISA dedicated to very particular tasks.
The program size of applications compiled for ERRIC is indeed often larger than
the same application compiled for other architectures.
The 16-bit instructions help to keep code size small, but the lack of direct
immediate support in instructions increases code size significantly. The lack of
some often used instructions, such as multiplications, also increases code size, as
the corresponding library calls need additional setup code. However, we consider
this as acceptable to keep the processor architecture simple.
The processor has a large register file with 32 32-bit wide general-purpose
registers. All normal instructions expect exactly two input registers and save the
result of the operation in the second register, therefore always overwriting the
second operand content. Memory access is only possible for 32 bit at a time and has
to be aligned.
The ERRIC processor has an internal state (F1, F2), which is required by the
special memory controller. The main philosophy of the ERRIC architecture is to
keep it simple, which is not only applied to the processor but also to the memory
controller. The processor and memory controller are designed not to stall the
processor due to pending memory operation.
This is achieved by interleaving instruction fetch and memory operations. All
ERRIC instructions are 16-bit wide; an instruction fetch operation therefore always
loads two instructions from memory and stores them in a processor internal
instruction register (IR).
In sequential instruction execution, the compiler can schedule memory
instructions in every second instruction slot where no instruction has to be loaded
by the processor. This concept is illustrated in Fig. 14.2, which shows an extended
version of Fig. 14.1 that includes memory operations.
In state F1, the processor fetches an instruction from memory, and the memory
unit is therefore busy in this cycle and cannot execute a memory operation at the
same time. If the processor is in state F2 (not in state F1), the processor can execute
a memory instruction. The compiler is responsible to schedule the instruction in
proper order.
If the executed instruction is a branch, the processor switches automatically to
the F1 state as the memory controller can only load 32-bit aligned addresses. Jump
destination locations must therefore also be 32-bit aligned. All these requirements
force the compiler to fill gaps with NOP operations.
The main structure of the processor architecture is shown in Fig. 14.3. The
instructions are fetched from memory into the instruction register and decoded by
the control unit, which also manages the execution of each instruction.
The operands for each executed instruction are fetched from either the register
file or memory, multiplexed into the Arithmetic and Logic Unit (ALU) for operation. The output data from the ALU go either to memory through the data bus or is
written back to the register file. The current value and type of the data might also
indicate an address for branch instructions.
14.1 Processor Architecture
199