processors, with the exception that no pipelining is used and therefore all steps of
one instruction are executed in one processor cycle and specially used memory
controller.
We briefly discuss the steps involved in the execution of one instruction.
Fetch Instruction This step loads an instruction from main memory and stores it
in the processor internal instruction register (IR). As every instruction is only 16-bit
wide (see Sect. 14.2), this step is needed every second instruction, if the instruction
is not a jump instruction.
Decode Instruction It decodes the instruction.
Execute Instruction It executes the instruction, i.e., calculates the result of
the instruction.
Store Result The instruction execution might have affected register content,
processor flags, and other processor state which is updated and written back in this
last step.
At first, it could be argued that the proposed ISA does not have enough
instructions to perform most of the operations that such a small ISA would result in
higher compilation effort/time, and that the resulting programs would need more
space.
Fig. 14.1 ERRIC instruction
execution—simple version
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14 Hardware: The ERRIC Architecture