Literaturverzeichnis
439
85. Caspi, P., Sangiovanni-Vincentelli, A., Almeida, L., et al: Guidelines for a graduate curriculum
on embedded software and systems. ACM Transactions on Embedded Computing Systems
pp. 587–611 (2005)
86. Castrillon, J., Tretter, A., Leupers, R., Ascheid, G.: Communication-aware mapping of
KPN applications onto heterogeneous MPSoCs. In: Proceedings of the Design Automation Conference (DAC), pp. 1266–1271. ACM, New York, NY, USA (2012). DOI
10.1145/2228360.2228597. URL http://doi.acm.org/10.1145/2228360.2228597
87. Cederqvist, P.: The CVS manual - version management with CVS. Network Theory Ltd.
(2006)
88. Ceng, J., Castrillón, J., Sheng, W., Scharwächter, H., Leupers, R., Ascheid, G., Meyr, H., Isshiki, T., Kunieda, H.: MAPS: an integrated framework for MPSoC application parallelization.
Proceedings of the Design Automation Conference (DAC) pp. 754–759 (2008)
89. Chamberlain, R., Taha, W., Törngren, M. (eds.): Cyber Physical Systems. Model-Based
Design – 2019 8th International Workshop, CyPhy 2018, and 14th International Workshop,
WESE 2018, Revised Selected Papers. Lecture Notes in Computer Science (2019)
90. Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low-power CMOS digital design. IEEE
Journal of Solid-State Circuits 27(4), 119–123 (1992)
91. Chanet, D., Sutter, B.D., Bus, B.D., Put, L.V., Bosschere, K.D.: Automated reduction of the
memory footprint of the Linux kernel. ACM Trans. Embed. Comput. Syst. 6(4), 23 (2007).
DOI http://doi.acm.org/10.1145/1274858.1274861
92. Chang, D.W., Lin, I.C., Chien, Y.S., Lin, C.L., Su, A.W.Y., Young, C.P.: CASA: ContentionAware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33(12),
1806–1817 (2014). DOI 10.1109/TCAD.2014.2363385
93. Chao, C., Saeta, B.: HotChips 2019 Tutorial – Cloud TPU: Codesigning Architecture and
Infrastructure. https://www.hotchips.org/hc31/HC31_T3_Cloud_TPU_Codesign.pdf (2019)
94. Chen, J., Huang, W., Liu, C.: k2Q: A Quadratic-Form Response Time and Schedulability
Analysis Framework for Utilization-Based Analysis. CoRR, http://arxiv.org/abs/1505.03883
(2015)
95. Chen, K., Sztipanovits, J., Neema, S.: Compositional specification of behavioral semantics.
Design, Automation and Test in Europe (DATE) pp. 906–911 (2007)
96. Chen, M., Rincón-Mora, G.: Accurate electrical battery model capable of predicting runtime
and i-v performance. IEEE Trans. on Energy Conversion pp. 504–511 (2006)
97. Chen, X., Dick, R., Shang, L.: Properties of and improvements to time-domain dynamic
thermal analysis algorithms. Proceedings of Design, Automation and Test in Europe (DATE)
(2010)
98. Chetto, H., Silly, M., Bouchentouf, T.: Dynamic scheduling of real-time tasks under precedence constraints. Journal of Real-Time Systems, 2 (1990)
99. Cheung, E., Hsieh, H., Balarin, F.: Automatic buffer sizing for rate-constrained KPN
applications on multiprocessor system-on-chip. In: High Level Design Validation and
Test Workshop, 2007. HLVDT 2007. IEEE International, pp. 37–44 (2007). DOI
10.1109/HLDVT.2007.4392782
100. Chiu, Y.: Folding and Interpolating ADC. University of Texas at Dallas, EECT 7327, http:
//www.utdallas.edu/~yxc101000/courses/7327/slides/intp%20folding%20adc.pptx (2014)
101. Cho, H., Ravindran, B., Jensen, E.: An optimal real-time scheduling algorithm for multiprocessors. Proceedings of the Real-Time Systems Symposium (RTSS) (2006)
102. Cho, S., Lee, S.K., Han, A., Lin, K.J.: Efficient real-time scheduling algorithms for multiprocessor systems. IEICE Trans. Communications pp. 2859–2867 (2002)
103. Chung, E.Y., Benini, L., De Micheli, G.: Source code transformation based on software
cost analysis. Proceedings of the International Symposium on System Synthesis (ISSS) pp.
153–158 (2001)
104. Clarke, E.M., Grumberg, O., Hiraishi, H., Jha, S., Long, D.E., McMillan, K.L., Ness, L.A.:
Verification of the Futurebus+ cache coherence protocol. Formal Methods in System Design
6(2), 217–232 (2005)
439
85. Caspi, P., Sangiovanni-Vincentelli, A., Almeida, L., et al: Guidelines for a graduate curriculum
on embedded software and systems. ACM Transactions on Embedded Computing Systems
pp. 587–611 (2005)
86. Castrillon, J., Tretter, A., Leupers, R., Ascheid, G.: Communication-aware mapping of
KPN applications onto heterogeneous MPSoCs. In: Proceedings of the Design Automation Conference (DAC), pp. 1266–1271. ACM, New York, NY, USA (2012). DOI
10.1145/2228360.2228597. URL http://doi.acm.org/10.1145/2228360.2228597
87. Cederqvist, P.: The CVS manual - version management with CVS. Network Theory Ltd.
(2006)
88. Ceng, J., Castrillón, J., Sheng, W., Scharwächter, H., Leupers, R., Ascheid, G., Meyr, H., Isshiki, T., Kunieda, H.: MAPS: an integrated framework for MPSoC application parallelization.
Proceedings of the Design Automation Conference (DAC) pp. 754–759 (2008)
89. Chamberlain, R., Taha, W., Törngren, M. (eds.): Cyber Physical Systems. Model-Based
Design – 2019 8th International Workshop, CyPhy 2018, and 14th International Workshop,
WESE 2018, Revised Selected Papers. Lecture Notes in Computer Science (2019)
90. Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low-power CMOS digital design. IEEE
Journal of Solid-State Circuits 27(4), 119–123 (1992)
91. Chanet, D., Sutter, B.D., Bus, B.D., Put, L.V., Bosschere, K.D.: Automated reduction of the
memory footprint of the Linux kernel. ACM Trans. Embed. Comput. Syst. 6(4), 23 (2007).
DOI http://doi.acm.org/10.1145/1274858.1274861
92. Chang, D.W., Lin, I.C., Chien, Y.S., Lin, C.L., Su, A.W.Y., Young, C.P.: CASA: ContentionAware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33(12),
1806–1817 (2014). DOI 10.1109/TCAD.2014.2363385
93. Chao, C., Saeta, B.: HotChips 2019 Tutorial – Cloud TPU: Codesigning Architecture and
Infrastructure. https://www.hotchips.org/hc31/HC31_T3_Cloud_TPU_Codesign.pdf (2019)
94. Chen, J., Huang, W., Liu, C.: k2Q: A Quadratic-Form Response Time and Schedulability
Analysis Framework for Utilization-Based Analysis. CoRR, http://arxiv.org/abs/1505.03883
(2015)
95. Chen, K., Sztipanovits, J., Neema, S.: Compositional specification of behavioral semantics.
Design, Automation and Test in Europe (DATE) pp. 906–911 (2007)
96. Chen, M., Rincón-Mora, G.: Accurate electrical battery model capable of predicting runtime
and i-v performance. IEEE Trans. on Energy Conversion pp. 504–511 (2006)
97. Chen, X., Dick, R., Shang, L.: Properties of and improvements to time-domain dynamic
thermal analysis algorithms. Proceedings of Design, Automation and Test in Europe (DATE)
(2010)
98. Chetto, H., Silly, M., Bouchentouf, T.: Dynamic scheduling of real-time tasks under precedence constraints. Journal of Real-Time Systems, 2 (1990)
99. Cheung, E., Hsieh, H., Balarin, F.: Automatic buffer sizing for rate-constrained KPN
applications on multiprocessor system-on-chip. In: High Level Design Validation and
Test Workshop, 2007. HLVDT 2007. IEEE International, pp. 37–44 (2007). DOI
10.1109/HLDVT.2007.4392782
100. Chiu, Y.: Folding and Interpolating ADC. University of Texas at Dallas, EECT 7327, http:
//www.utdallas.edu/~yxc101000/courses/7327/slides/intp%20folding%20adc.pptx (2014)
101. Cho, H., Ravindran, B., Jensen, E.: An optimal real-time scheduling algorithm for multiprocessors. Proceedings of the Real-Time Systems Symposium (RTSS) (2006)
102. Cho, S., Lee, S.K., Han, A., Lin, K.J.: Efficient real-time scheduling algorithms for multiprocessor systems. IEICE Trans. Communications pp. 2859–2867 (2002)
103. Chung, E.Y., Benini, L., De Micheli, G.: Source code transformation based on software
cost analysis. Proceedings of the International Symposium on System Synthesis (ISSS) pp.
153–158 (2001)
104. Clarke, E.M., Grumberg, O., Hiraishi, H., Jha, S., Long, D.E., McMillan, K.L., Ness, L.A.:
Verification of the Futurebus+ cache coherence protocol. Formal Methods in System Design
6(2), 217–232 (2005)