438
Literaturverzeichnis
62. Bouwmeester, D., Ekert, A., (eds.), A.Z.: The Physics of Quantum Information: Quantum
Cryptography, Quantum Teleportation, Quantum Computation. Springer (2000)
63. Bouyssounouse, B., Sifakis, J. (eds.): Embedded Systems Design, The ARTIST Roadmap for
Research and Development. Lecture Notes in Computer Science, Vol. 3436, Springer (2005)
64. Brahme, D., Abraham, J.A.: Functional testing of microprocessors. IEEE Trans. on Computers
pp. 475–485 (1984)
65. Brand, D., Bergamaschi, R.A., Stok, L.: Don’t cares in synthesis: theoretical pitfalls and
practical solutions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems 17(4), 285–304 (1998). DOI 10.1109/43.703819
66. Braun, A., Bringmann, O., Lettnin, D., Rosenstiel, W.: Simulation-based verification of the
MOST netinterface specification revision 3.0. Proceedings of Design, Automation and Test
in Europe (DATE) (2010)
67. Bremaud, P.: Markov Chains. Springer (1999)
68. Brettel, M., Friederichsen, N., Keller, M., Rosenberg, M.: How virtualization, decentralization
and network building change the manufacturing landscape: An industry 4.0 perspective.
International Journal of Mechanical, Industrial Science and Engineering 8(1), 37–44 (2014)
69. Bril, R.J.: Real-time scheduling for media processing using conditionally guaranteed budgets.
PhD thesis, TU Eindhoven (2004)
70. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power
analysis and optimizations. 27th Int. Symp. on Computer Architecture (ISCA) pp. 83–94
(2000)
71. Bruno, E., Bollella, G.: Real-Time Java Programming: With Java RTS. Prentice Hall (2009)
72. Bryant, R.: A switch-level model and simulator for MOS digital circuits. IEEE Trans. on
Computers, Vol. 33 (1984)
73. Buck, J.T.: Scheduling dynamic dataflow graphs with bounded memory using the token flow
model. Ph.D. thesis, University of California at Berkeley (1993)
74. Budkowski, S., Dembinski, P.: An introduction to Estelle: A specification language for distributed systems. Computer Networks and ISDN Systems 14(1), 3 – 23 (1987). DOI
DOI:10.1016/0169-7552(87)90084-5. URL https://www.sciencedirect.com/science/article/
pii/0169755287900845?via%3Dihub
75. Bundesamt für Sicherheit in der Informationstechnik: IT-Grundschutz – Glossar.
https://www.bsi.bund.de/DE/Themen/ITGrundschutz/ITGrundschutzKompendium/
vorkapitel/Glossar_.html (2021)
76. Burd, T., Brodersen, R.: Design issues for dynamic voltage scaling. Int. Symp. on Low Power
Electronics and Design (ISLPED) pp. 9–14 (2000)
77. Burd, T., Brodersen, R.W.: Energy efficient microprocessor design. Kluwer Academic Publishers (2003)
78. Burks, A., Goldstine, H., von Neumann, J.: Preliminary discussion of the logical design of
an electronic computing element. Report to U.S. Army Ordnance Department, reprinted at
https://www.cs.princeton.edu/courses/archive/fall10/cos375/Burks.pdf (1946)
79. Burns, A., Wellings, A.: Real-Time Systems and Programming Languages. Addison-Wesley
(1990)
80. Burns, A., Wellings, A.: Real-Time Systems and Programming Languages (Fourth Edition).
Addison Wesley (2009)
81. Buttazzo, G.: Hard Real-time Computing Systems. Springer, 4th printing (2011)
82. Cadence Design Systems Inc.: Tensilica Customizable Processor IP. http://ip.cadence.com/
ipportfolio/tensilica-ip (2021)
83. Cai, L., Gajski, D.: Transaction level modeling: An overview. In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS),
pp. 19–24. ACM, New York, NY, USA (2003). DOI 10.1145/944645.944651. URL
http://doi.acm.org/10.1145/944645.944651
84. Carroll, A., Heiser, G.: An analysis of power consumption in a smartphone. In: Proceedings of
the 2010 USENIX Conference on USENIX Annual Technical Conference, USENIXATC’10,
pp. 21–21. USENIX Association, Berkeley, CA, USA (2010). URL http://dl.acm.org/citation.
cfm?id=1855840.1855861
Literaturverzeichnis
62. Bouwmeester, D., Ekert, A., (eds.), A.Z.: The Physics of Quantum Information: Quantum
Cryptography, Quantum Teleportation, Quantum Computation. Springer (2000)
63. Bouyssounouse, B., Sifakis, J. (eds.): Embedded Systems Design, The ARTIST Roadmap for
Research and Development. Lecture Notes in Computer Science, Vol. 3436, Springer (2005)
64. Brahme, D., Abraham, J.A.: Functional testing of microprocessors. IEEE Trans. on Computers
pp. 475–485 (1984)
65. Brand, D., Bergamaschi, R.A., Stok, L.: Don’t cares in synthesis: theoretical pitfalls and
practical solutions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems 17(4), 285–304 (1998). DOI 10.1109/43.703819
66. Braun, A., Bringmann, O., Lettnin, D., Rosenstiel, W.: Simulation-based verification of the
MOST netinterface specification revision 3.0. Proceedings of Design, Automation and Test
in Europe (DATE) (2010)
67. Bremaud, P.: Markov Chains. Springer (1999)
68. Brettel, M., Friederichsen, N., Keller, M., Rosenberg, M.: How virtualization, decentralization
and network building change the manufacturing landscape: An industry 4.0 perspective.
International Journal of Mechanical, Industrial Science and Engineering 8(1), 37–44 (2014)
69. Bril, R.J.: Real-time scheduling for media processing using conditionally guaranteed budgets.
PhD thesis, TU Eindhoven (2004)
70. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power
analysis and optimizations. 27th Int. Symp. on Computer Architecture (ISCA) pp. 83–94
(2000)
71. Bruno, E., Bollella, G.: Real-Time Java Programming: With Java RTS. Prentice Hall (2009)
72. Bryant, R.: A switch-level model and simulator for MOS digital circuits. IEEE Trans. on
Computers, Vol. 33 (1984)
73. Buck, J.T.: Scheduling dynamic dataflow graphs with bounded memory using the token flow
model. Ph.D. thesis, University of California at Berkeley (1993)
74. Budkowski, S., Dembinski, P.: An introduction to Estelle: A specification language for distributed systems. Computer Networks and ISDN Systems 14(1), 3 – 23 (1987). DOI
DOI:10.1016/0169-7552(87)90084-5. URL https://www.sciencedirect.com/science/article/
pii/0169755287900845?via%3Dihub
75. Bundesamt für Sicherheit in der Informationstechnik: IT-Grundschutz – Glossar.
https://www.bsi.bund.de/DE/Themen/ITGrundschutz/ITGrundschutzKompendium/
vorkapitel/Glossar_.html (2021)
76. Burd, T., Brodersen, R.: Design issues for dynamic voltage scaling. Int. Symp. on Low Power
Electronics and Design (ISLPED) pp. 9–14 (2000)
77. Burd, T., Brodersen, R.W.: Energy efficient microprocessor design. Kluwer Academic Publishers (2003)
78. Burks, A., Goldstine, H., von Neumann, J.: Preliminary discussion of the logical design of
an electronic computing element. Report to U.S. Army Ordnance Department, reprinted at
https://www.cs.princeton.edu/courses/archive/fall10/cos375/Burks.pdf (1946)
79. Burns, A., Wellings, A.: Real-Time Systems and Programming Languages. Addison-Wesley
(1990)
80. Burns, A., Wellings, A.: Real-Time Systems and Programming Languages (Fourth Edition).
Addison Wesley (2009)
81. Buttazzo, G.: Hard Real-time Computing Systems. Springer, 4th printing (2011)
82. Cadence Design Systems Inc.: Tensilica Customizable Processor IP. http://ip.cadence.com/
ipportfolio/tensilica-ip (2021)
83. Cai, L., Gajski, D.: Transaction level modeling: An overview. In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS),
pp. 19–24. ACM, New York, NY, USA (2003). DOI 10.1145/944645.944651. URL
http://doi.acm.org/10.1145/944645.944651
84. Carroll, A., Heiser, G.: An analysis of power consumption in a smartphone. In: Proceedings of
the 2010 USENIX Conference on USENIX Annual Technical Conference, USENIXATC’10,
pp. 21–21. USENIX Association, Berkeley, CA, USA (2010). URL http://dl.acm.org/citation.
cfm?id=1855840.1855861