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42. Benavides, T., Treon, J., Hulbert, J., Chang, W.: The enabling of an execute-in-place architecture to reduce the embedded system memory footprint and boot time. JCP 3(1), 79–89
(2008). DOI 10.4304/jcp.3.1.79-89. URL http://dx.doi.org/10.4304/jcp.3.1.79-89
43. Bender, A.: MILP based task mapping for heterogeneous multiprocessor systems. In: Design
Automation Conference, 1996, with EURO-VHDL ’96 and Exhibition, Proceedings EURODAC ’96, European, pp. 190–197 (1996). DOI 10.1109/EURDAC.1996.558204
44. Bengtsson, J., Yi, W.: Timed automata: Semantics, algorithms and tools. In: J. Desel, W.
Reisig and G. Rozenberg (eds.): ACPN 2003, Springer LNCS 3098, 87–124 (2004)
45. Benini, L., Bogliolo, A., De Micheli, G.: A survey of design techniques for system-level
dynamic power management. IEEE Transactions on VLSI Systems 8(3), 299–316 (2000)
46. Benini, L., De Micheli, G.: Dynamic Power Management – Design Techniques and CAD
Tools. Kluwer Academic Publishers (1998)
47. van Berkel, C.H.K.: Multi-core for mobile phones. In: Proceedings of the Conference on
Design, Automation and Test in Europe, DATE ’09, pp. 1260–1265. European Design and
Automation Association, 3001 Leuven, Belgium, Belgium (2009). URL http://dl.acm.org/
citation.cfm?id=1874620.1874924
48. Bernardi, P., Rebaudengo, M. Reorda, S.: Using infrastructure IPs to support SW-based selftest of processor cores. Workshop on Fibres and Optical Passive Components pp. 22–27
(2005)
49. Bernstein, J.B., Gurfinkel, M., Li, X., Walters, J., Shapira, Y., Talmor, M.: Electronic circuit
reliability modeling. Microelectronics Reliability 46(12), 1957 – 1979 (2006). DOI http://dx.
doi.org/10.1016/j.microrel.2005.12.004. URL http://www.sciencedirect.com/science/article/
pii/S0026271406000023
50. Bertogna, M., Cirinei, M., Lipari, G.: Improved schedulability analysis of EDF on multiprocessor platforms. In: Euromicro Conference on Real-Time Systems (ECRTS), pp. 209–218
(2005). DOI 10.1109/ECRTS.2005.18
51. Bertolotti, I.C.: Real-time embedded operating systems: Standards and perspectives. In: R.
Zurawski (ed.): Embedded Systems Handbook, CRC Press (2006)
52. Beszedes, A.: Survey of code size reduction methods. ACM Computing Surveys pp. 223–267
(2003)
53. Bieker, U., Marwedel, P.: Retargetable self-test program generation using constraint logic
programming. Proceedings of the Design Automation Conference (DAC) pp. 605–611 (1995)
54. Bini, E., Buttazzo, G., Buttazzo, G.: A hyperbolic bound for the rate monotonic algorithm.
Euromicro Conference on Real-Time Systems (ECRTS) pp. 59–73 (2001)
55. Black, J.R.: Electromigration failure modes in aluminum metallization for semiconductor
devices. Proceedings of the IEEE 57(9), 1587–1594 (1969). DOI 10.1109/PROC.1969.7340
56. Boldt, M., Traulsen, C., von Hanxleden, R.: Compilation and Worst-case Reaction Time
Analysis for Multithreaded Esterel Processing. EURASIP J. Embedded Syst. 2008, 4:1–4:21
(2008). DOI 10.1155/2008/594129. URL http://dx.doi.org/10.1155/2008/594129
57. Bonfietti, A., Benini, L., Lombardi, M., Milano, M.: An efficient and complete approach for
throughput-maximal SDF allocation and scheduling on multi-core platforms. In: Proceedings
of Design, Automation and Test in Europe (DATE), pp. 897–902. European Design and
Automation Association, 3001 Leuven, Belgium, Belgium (2010). URL http://dl.acm.org/
citation.cfm?id=1870926.1871143
58. Bonny, T., Henkel, J.: Huffman-based code compression techniques for embedded processors.
ACM Trans. Des. Autom. Electron. Syst. 15(4), 31:1–31:37 (2010). DOI 10.1145/1835420.
1835424. URL http://doi.acm.org/10.1145/1835420.1835424
59. Bordoloi, U.: Scheduling with shared resources.
Ursprüngliche Adresse:
http://www.ida.liu.se/~unmbo/RTS_CUGS_files/Lecture3.pdf, z.Zt. (2021) verfügbar
unter https://tams.informatik.uni-hamburg.de/lehre/2016ss/vorlesung/es/doc/ida.liu.se-rtsLecture3.pdf (2020)
60. Boulanger, J.L.: CENELEC 50128 and IEC 62279 Standards. John Wiley & Sons (2015)
61. Boussinot, F., de Simone, R.: The Esterel language. Proc. of the IEEE, Vol. 79, No. 9 pp.
1293–1304 (1991)