4
Evaluation of Network-on-Chip
Architectures
4.1 Evaluation Methodologies of NoC
This section presents the strategy to evaluate the performance and cost of
networks-on-chip (NoCs). In the NoC paradigm, while evaluating the performance of an interconnect infrastructure, its energy consumption profile
and silicon area overhead must also be considered, as it can be a significant
portion of the overall system-on-chip (SoC) cost budget. It has been reported
in the work of Pande et  al. (2005) that Scalable, Programmable Integrated
Network (SPIN) and octagon network have very high throughput, but their
energy consumption and silicon area overhead are much higher than both
mesh and butterfly fat tree (BFT). Folded torus shows almost similar results
like mesh. In the deep submicron (DSM) era where high-performance and
low-power design is a major goal, for a NoC designer it is always preferable
to choose a topology with lower average energy per packet profile. Taking
this fact into consideration, mesh topology is widely used in academia and
industry.
In this chapter, a thorough comparative study of performance evaluation,
estimation of energy consumptions and area overhead of different meshand tree-based NoC topologies have been shown with the same number of
intellectual property (IP) cores under the same bisection width constraint as
reported in Kundu et al. (2012). A bisection width is defined as the minimum
number of wires to be removed in order to bisect the network into two equal
halves. A network with higher bisection width is expected to show better
performance. This chapter considers two variants of mesh structure—one
core and two cores connected to each router, BFT, and mesh-of-tree (MoT)
network structures—and compares their performance and cost for a 32-corebased system. The bisection width of all the above networks is taken as 4.
Each IP core has been inserted into a tile of dimension 2.5 mm × 2.5 mm,
similar to that discussed in the work of Feero and Pande (2009).
Although the total chip area can be obtained only after layout, Figures 4.1
through 4.4 show the possible distributions of cores, routers, and links for
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