74
Network-on-Chip
Jiang, H. J. 2004. Scalable gray code counter and applications thereof. U.S. Patent
6762701, July 13, 2004.
Kavaldjiev, N., Smit, G. J. M., Jansen, P. G., and Wolkotte, P. T. 2006. A virtual channel network-on-chip for GT and BE traffic. Proceedings of IEEE Computer Society
Annual Symposium on Emerging VLSI Technologies and Architectures, March 2–3,
Karlsruhe, Germany.
Kumar, A., Kundu, P., Singh, A. P., Peh, L. S., and Jha, N. K. 2007. A 4.6Tbits/s
3.6GHz single-cycle NoC router with a novel switch allocator in 65nm
CMOS. Proceedings of IEEE International Conference on Computer Design,
pp. 63–70, October 7–10, Lake Tahoe, CA.
Kundu, S. and Chattopadhyay, S. 2008. Network-on-chip architecture design based
on mesh-of-tree deterministic routing topology. International Journal for High
Performance Systems Architecture, Inderscience Publishers, vol. 1, no. 3, pp. 163–182.
Kundu, S., Soumya, J., and Chattopadhyay, S. 2012. Design and evaluation of meshof-tree based network-on-chip using virtual channel router. Microprocessors and
Microsystems Journal, vol. 36, pp. 471–488.
Mullins, R., West, A., and Moore, S. 2004. Low-latency virtual-channel routers for onchip networks. Proceedings of 31st Annual International Symposium on Computer
Architecture, pp. 188–197, June 19–23, Munich, Germany.
Mullins, R., West, A., and Moore, S. 2006. The design and implementation of a lowlatency on-chip network. Proceedings of Asia and South Pacific Design Automation
Conference, pp. 164–169, January 24–27, Yokohama, Japan.
Peh, L.-S. and Dally, W. J. 2001. A delay model and speculative architecture for
pipelined routers. Proceedings of International Symposium on High-Performance
Computer Architecture, pp. 255–266, Monterrey, Mexico.