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Network-on-Chip
The rok signals from each input channel module are used as input signals
to a (P – 1)*V:1 MUX. The number of MUXes used in each switch allocator
module is V. From the VC allocator module, when ce_1 is set, the encoder output selects the corresponding rok signal. For example, rok1 is selected if gnt1
is set, rok2 is selected if gnt2 is set, and so on. Now if the full signal coming
from the first VC of the next router’s input link is at logic 0 and the status bit
b_1 is at logic 1, the ready_vc_1 signal becomes set, which signifies that this
VC is ready to accept the incoming flits. This signal is used as an input to the
V:1 round-robin arbiter to access the outgoing physical link. In the same way,
the other inputs of the arbiter (ready_vc_2, ready_vc_3, etc.) can send requests
to access the outgoing physical link. Depending on the winner of the arbitration process, the encoder module generates the encoded_vc_id signal. For
example, encoded_vc_id  = 00 for gnt_vc_1  = 1, encoded_vc_id  = 01 for gnt_
vc_2 = 1, and so on. These encoded_vc_id bits are used to select the incoming
flits to access the outgoing physical channel as shown in Figure 3.16. It also
overwrites the existing vc_id bits such that the outgoing flits will be written
into a newly allocated VC of the next router’s input link module. The arbiter
output signals are also used as rd_en signals to the IRS block of each input
channel module.
The router is designed in Verilog HDL and synthesized in Synopsys Design
Vision supporting 90-nm CMOS technology with Faraday library to generate
a gate-level netlist. For a leaf router in the MoT-based network having a node
degree of 4, a synthesis of the design shows that the critical path lies from
the IB to (P – 1)*V input arbiter inside the VC allocator module and the delay
of the critical path is found to be 600  ps. Hence, the router can operate at
1.66  GHz. The overall router architecture has four-cycle latency, one cycle
each in FIFO, (P – 1)*V input arbiter of the VC allocator, status register of the
VC allocator module, and V:1 arbiter of the switch allocator module.
3.7 Adaptive Router Architecture Design
A number of adaptive router architectures for NoC have been proposed
in the literature. Among these architectures, this chapter adopts the work
cited by Hu and Marculescu (2004a) for its simplicity in implementation. The
authors proposed a dynamic adaptive–deterministic (DyAD) routing for a
2D mesh. DyAD is a new paradigm for NoC router design that exploits the
advantages of deterministic and adaptive routing. Indeed, based on this
idea, any suitable deterministic and adaptive routing scheme can be combined to form a DyAD router (although care must be taken for issues such
as deadlock freedom). DyAD selects minimal odd–even routing as the adaptive routing and XY routing as the deterministic routing. The odd–even is
able to achieve much higher saturation throughput compared to XY routing.