gnt1
gnt2
OR
gnt(P−1)*V
gnt_or
gnt1 ce_1
ce_V
S_V
S_1
reg_1
D
ce
D
ce
rd_clk
clr_1
b_1
b_1
b_1
b_2
b_V
b_2
rd_clk
clr_V
clr_V
clr_1
D
Vcc
Vcc
Vcc
clr_2
b_V
b_2
b_1
Q
ce
ce_V
ce_1
ce_2
ce
D Q
D
Status
register
ce
Q
reg_V
gnt2
gnt3
E
n
c
o
d
e
r
gnt4
g4
Control
logic
Control
logic
MUX_V
All tailer signals
All tailer Signals
MUX_1
AND
all_vc_busy
g3
g2
g1
AND
AND
AND
AND
(P–1)*V
input arbiter
g1

req1

g2

req2

g3

req3

g4

req4

68
Network-on-Chip
.
le
u
d
o
5
r m
1
o
.
e 3
t
a
c
o
r
l
u
l
ig
C a
F
V