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Architecture Design of Network-on-Chip
all_vc_busy
req_1
req_v
req_1
req_v
Arbiter
Arb1
Arb
(P–1)
V:1
gnt_1
gnt_v
gnt_1
gnt_v
(P−1):1
V:1
Figure 3.14
(P – 1)*V input tree arbiter.
signal (gnt1) is at logic 1. The g1 signal is latched at logic 0 one clock cycle
after the gnt1 becomes high. It remains at logic 0until req1 is reset to 0. Thus,
gnt1 signal will remain high for one clock cycle. As the arbiter selects a single
request signal at a time, no two grant signals will overlap with each other.
The encoder module encodes all the grant signals. The width of the encoder
output signal is log 2 [(P − 1) * V].
To store the status of each VC of the next router’s input link module, a
V-bit status register is used. Each bit (b_1, b_2, etc.) signifies whether the corresponding VC of the next router’s input link is engaged or not. The status
register has been implemented using D-type flip-flops. Initially, all the D flipflops are reset. Hence, b_1 = b_2 = … = b_v = 0 and ce_1 = ce_2 = … = ce_v = 0.
Now, if any grant signal is high, the ce_1 signal is set; as a result, b_1 gets
latched at logic-1. When a particular status register is set by a grant signal, it
will remain high until the tailer of the corresponding packet comes. The tailer
signal from each input channel module is used as an input to a (P – 1)*V:1
MUX. The number of MUXes used in each VC allocator module is V. When
ce_1 is set, the encoder output selects the corresponding tailer signal. For
example, tailer1 is selected if gnt1 is set, tailer2 is selected if gnt2 is set, and
so  on. This selected tailer signal is used to reset the individual bits of the