data-in
wr-en
wr-clk
rd-clk
rd-en
full
empty
rok (to all o/p links)
rd-en signals
data
to crossbar
from all o/p links
dout
reset
IB
RC
IRS
Tailer
DFF
tailer
(to all o/p links)
Header
ce
clk
rd-clk
din
request
to crossbar
66
Network-on-Chip
Figure 3.13
Input channel module for VC router.
3.6.2 Output Links
The output link module consists of two major architectural components—
VC allocator and switch allocator. These two components are briefly described
in Sections 3.6.2.1 and 3.6.2.2.
3.6.2.1 VC Allocator
In the generic VC router architecture (Mullins et al. 2004), VC allocator needs
two stages of arbitration. The first stage has a V:1 arbiter at each input VC,
followed by a second stage of P*V:1 arbiters for each output VC. In the modified router architecture (Figure 3.12), as all the request signals from each input
channel are coming to the crossbar, the first-stage arbiters are eliminated. The
number of request signals reaching each output link module is (P – 1)*V. Thus,
in each output link module, a (P – 1)*V input arbiter is required. For designing
an arbiter with such a large number of inputs, a tree of smaller arbiters is used.
A single (P – 1)*V input arbiter is replaced by a single (P – 1) input arbiter and
(P – 1) groups of V input arbiters. Each V input arbiter arbitrates in a roundrobin fashion between the incoming requests from different input channels of
a specific input link module. The (P – 1) input arbiters select the winner of them
in a round-robin fashion, thus selecting a single request at a time from a set of
(P – 1)*V inputs. The implementation of a (P – 1)*V input tree arbiter is shown in
Figure 3.14. The all_vc_busy signal has the control to reset all the grant signals.
The VC allocator module uses the above tree arbiter to allocate the VCs.
Figure 3.15 depicts the overall VC allocator architecture. The outputs of the
control logic module (g1, g2, g3, etc.) are ANDed with the incoming request
signals. Initially, gnt1 = gnt2 = gnt3 = … = 0, and g1 = g2 = g3 = … = 1. Now,
if any of the request signals (say req1) is granted, the corresponding grant