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Network-on-Chip
with its data, framing, and flow control signals. Each channel includes n bits
for data and two bits for packet framing (eop and bop) as shown in Figure 3.6.
The flow control signals are used for the following (as shown in the figure).
• To request for incoming data (in-req) from the previous module
• To request for outgoing data (out-req) from the present module
• To validate the incoming (in-val) data
• To validate the outgoing (out-val) data
Next, we look into the circuitry inside the wormhole routers. The router consists of instances of two kinds of modules: input channel and output channel. A brief description of each module is given in the following section.
3.5.1 input Channel Module
Each input channel module is composed of four architectural blocks as
shown in Figure 3.7: (1) input flow controller (IFC), (2) input FIFO buffer (IB),
(3) routing computation (RC) unit, and (4) input read switch (IRS).
The IFC block implements the logic that performs the translation between
the handshake and the FIFO flow control protocols. It sends in-req signal to
the previous router when its FIFO is not full. The in-req signal is connected
with the out-req port of the output channel of the previous router. If the
incoming flit is valid (in-val = 1) and FIFO is not full, flit will be written into
the FIFO buffer synchronously with the wr-clk. The in-val signal is coming
from the out-val port of the output channel of the previous router.
The IB block is designed as mentioned in Section 3.3. Data (data-out) is coming
out from the FIFO synchronously with the router’s own clock (router-clk).
The RC unit performs the routing function. It detects the header from the
outgoing flits of FIFO and runs the routing algorithm to select an output channel. After detecting the header, it sends a request to one of the output channels.
The selected output channel, in turn, sends a grant signal to that request, when
it is free. This grant signal comes to the IRS block of the input channel module.
The input channel module also sends a read-ok signal to the selected output
channel. The read-ok signal is turned high if the outgoing flit is a valid one. The
request signal remains high until the tailer comes out from FIFO.
The IRS block receives three x-RD signals and three x-gnt signals from other
output channel modules (Figure  3.7) and generates a granted read enable
signal (rd-en) for reading from FIFO, provided that the FIFO is not empty.
3.5.2 Output Channel Module
Each output channel consists of four blocks: (1) switch arbiter (SA), (2) output flow control (OFC), (3) output read switch (ORS), and (4) output FIFO
buffer (OB).