data_in
wr_en & ! FULL
wr_clk
wr_clk
wr_addr
reset
reset
reset
reset
rd_clk
rd_addr
wr_clk
rd_clk
Write counter
Read counter
wr_ptr
wr_dir
FULL
rd_ptr
rd_dir rd_clk
D
D
Q
Q
D
D
Q
Q
wr_dir
rd_dir
wr_ptr
rd_ptr
asynch_full asynch_empty
EMPTY
Synchronizer
Synchronizer
Asynchronous comparator
FIFO memory
din
data_out
data_out
wr_en
rd_en
rd_en & ! EMPTY
data_in
din
dout
reset
wr_clk
wr_en
din
dout
reset
wr_clk
wr_en
din
dout
reset
wr_clk
wr_en
din
dout
reset
wr_clk
wr_en
rd_addr
rd_clk
rd_en
reset
din
dout
reset
wr_clk
wr_en
din
dout
reset
wr_clk
wr_en
reset
(wr_en &
wr_addr [000])
(wr_en &
wr_addr [001])
(wr_en &
wr_addr [011])
(wr_en &
wr_addr [111])
(wr_en &
wr_addr [101])
(wr_en &
wr_addr [100])
wr_clk
data_out
din
dout
rd_clk
rd_en
reset
56
Network-on-Chip
Figure 3.3
Dual-clock asynchronous FIFO.
Figure 3.4
Design of FIFO memory.