55
Architecture Design of Network-on-Chip
Method 1
Method 2
000
001
011
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110
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011
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Skipped
Figure 3.2
Scalable gray coding scheme.
are two ways to solve the problem if the difference is even. One method is to
compute (2 m – N)/2 and skip these many locations from the top and the bottom. The other method is to skip these many locations on both sides from the
center. These two techniques are shown in Figure 3.2 for a mod-6 gray code.
However, this scalable gray code concept fails if (2 m – N) is odd (e.g., N = 5).
In this chapter, FIFO depth has been taken as 6 where the patterns 010 and
110 are skipped to get a mod-6 gray counter.
The block diagram of FIFO with a gray-code counter is shown in Figure 3.3.
The FIFO memory has been designed as a stack of six write registers followed
by a 6:1 multiplexer (MUX) and a single read register as shown in Figure 3.4.
In the FIFO, read and write counters are two separate gray counters, synchronous with read and write clocks, respectively. The write pointer denotes the
position to where the next incoming flit will be written and the read pointer
denotes the position from where a flit will be read next. Initially write direction
(wr_dir) and read direction (rd_dir) signals are reset. The individual direction
bits are getting inverted if the respective counter wraps around after reaching
the maximum count.
Asynchronous comparator module compares the write and read pointers and
generates the asynchronous full and empty signals. This module contains
only a combinational comparison logic. The functionality of the asynchronous comparator module is as follows:
full = ((wr_addr = = rd_addr) && (wr_dir ! = rd_dir))
empty = ((wr_addr = = rd_addr) && (wr_dir = = rd_dir))
These asynchronous full and empty signals are synchronized by write clock
and read clock, respectively, to generate FULL and EMPTY signals. Here,
two D flip-flops (marked as synchronizer in Figure 3.3) are cascaded to reduce
the probability of metastability. An attempt to read from an empty FIFO produces an invalid data at the output port.
