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Network-on-Chip
As the routers and IP cores are operated by independent clocks, the asynchronous FIFO in NI performs the synchronization task in clock domain
crossing. Apart from the above services, NI also performs cache coherency
by implementing directory-based protocols (Acacio et al. 2004).
2.8 Summary
This chapter presents different aspects of NoC design. It has been observed
that the 2D mesh topology with wormhole packet switching and deterministic routing is the most common and widely used in academia and industry
so far. Besides mesh architecture, this chapter also considers MoT topology
as an example and shows an addressing scheme and a deterministic routing strategy in it. It proves that the MoT-based network, with the proposed
routing algorithm, is always livelock and deadlock free. It also proves that
the packets will always follow a specific shortest path from source to destination. The number of edges of an M × N MoT graph and the average distance
of the network have been formulated. It has been shown that the network
can achieve the maximum throughput and the minimum latency when the
number of row trees and that of column trees are equal.
Toward the design of a complete NoC-based SoC, Chapter 3 presents the
design of wormhole and VC router architecture in detail.
References
Acacio, M. E., Gonzalez, J., Garcia, J. M., and Duato, J. 2004. An architecture for
high-performance scalable shared-memory multiprocessors exploiting on-chip
integration. IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 8,
pp. 755–768.
Agarwal, A., Iskander, C., and Shankar, R. 2009. Survey of network on chip (NoC)
architectures and contribution. Journal of Engineering, Computing, and Architecture,
vol. 3, no. 1.
Andreasson, D. and Kumar, S. 2004. On improving best-effort throughput by better
utilization of guaranteed-throughput channels in an on-chip communication
system. Proceedings of the IEEE Norchip Conference, pp. 265–268, Oslo, Norway.
Ascia, G., Catania, V., Palesi, M., and Patti, D. 2008. Implementation and analysis
of a new selection strategy for adaptive routing in networks-on-chip. IEEE
Transactions on Computers, vol. 57, no. 6, pp. 809–820.
Balfour, J. and Dally, W. J. 2006. Design tradeoffs for tiled CMP on-chip networks.
Proceedings of the ACM International Conference on Supercomputing (ICS),
pp. 187–198, Christchurch, New Zealand.