Application core
Core-specific wrapper
Generic core interface
Network interface
PM
PD
Asynchronous FIFO
Asynchronous FIFO
PM FIFO
PD FIFO
PM
Memory
PD
Memory
Read module
Header
Write module
Header
Router
47
Interconnection Networks in Network-on-Chip
Figure 2.27
The NI architecture.
a. It packetizes the message stored in PM memory and breaks them
into several flits (such as header, payload, tailer, and invalid flits)
before queuing them into asynchronous FIFO having independent read and write clocks.
b. In case of source routing, NI maintains the routing information
in a look-up table.
c. It inserts redundant bits (parity or cyclic redundancy [CRC]) in
the packet tailer for supporting end-to-end flow control with
proper retransmission mechanism.
3. PD: It performs the following tasks at the destination core:
a. It writes the incoming flits from the asynchronous FIFO to the
PD memory.
b. It decodes the packet header from the PD memory, extracts
the   control information required by the core, and passes it
to  GCI.
c. The core wrapper reads the payload and tailer from the PD memory to obtain the total message. It also performs error detection
for end-to-end flow control.
d. It ensures in-order delivery of packets, which is extremely important for adaptive routing.