20
Network-on-Chip
Figure 2.8
A 2D binary tree network with four cores to each leaf level router.
Number of routers required: (N/2 − 1)
Node degree: 5 (leaf), 3 (stem), 2 (root)
A fat tree-based generic interconnect template called Scalable, Programmable
Integrated Network (SPIN) has been proposed for on-chip interconnection
(Guerrier and Greiner 2000). Every node has four children and the parent is
replicated four times at any level of the tree as shown in Figure 2.9. The functional IP blocks reside at the leaves and the switches reside at the vertices.
The disadvantages of a fat tree architecture are its large switch size and high
node degree. A fat tree-based network with N IP blocks (N = 2 i , where i = 4,
5, 6, . . .) has the following parameters:
Diameter: 2 × (⎡ ⎢ (log 2 N)/ 2⎤ ⎥ ) − 2

Bisection width: N/2 when i is even, N/4 when i is odd

Figure 2.9
A 2D SPIN network with four cores to each level router.