360
Index
Asynchronous FIFO design, 54–56
dual-clock, 56f
FIFO memory, 56f
scalable gray code concept, 55, 55f
Automated test equipment (ATE), 245
Automated test pattern generation
(ATPG), 239
Average overall latency (L avg ), 80
under localized traffic
in 3D NoC with self-similar
traffic, 342–345, 342t, 343f, 344f
in MoT with VC router, 110–111,
110f, 111f, 112f
MoT with WH router
at different locality factors,
86–87, 87f
under localized traffic, 99–101, 99t,
100f, 101f
B
Bandwidth (BW), 80
utilization, 311
Best effort (BE) service, 45–46
Best fit decreasing (BFD) heuristics, 247
BI Hamming (BIH) code, 223
Binary and gray coding scheme,
170, 170t
Binomial mapping (BMAP), 129
flowchart, 130f
OCN design flow in, 129f
stages of OCN synthesis process
in, 129
Bisection width, 75
Bit error (ε), probability, 228
Bit error rate (BER), 174, 228, 228f
Bose–Chaudhuri–Hocquenghem (BCH)
code, 220
Boundary shift code (BSC), 224
Built-in self-repair (BISR)
mechanism, 204
Built-in self-test (BIST), 254, 257
Built-in soft error resilience (BISER)
technique, 206
Burst word error, probability, 229
Bus-invert (BI) code, 168, 222
hardware of, 168, 169f
scheme with 8-bit data bus, 169t
Butterfly fat tree (BFT) network, 75, 325
2D, 21, 21f
3D, 333, 334f
distribution of cores, routers, and
links in, 77f
router classification, 76
C
Capacitive crosstalk avoidance
techniques
CAC, 212–216
driver strength, 211
increase inter-wire spacing, 211
OCS, 211–212
usage of shielding and duplicating
wire, 210, 211t
Channel direction control (CDC)
protocol, 311
Channel power consumption, 255
Channel width and flit size, selection, 84
Chip-Level Integration of
Communicating
Heterogeneous Elements
(CLICHÉ), 14–15
Chip multiprocessing (CMP)
system, 1, 9
Clustering-based approach, 276f
Communication cost (fitness), 282
Communication dependence
and computation model
(CDCM), 138
Communication fabric, testing, 236–244
NoC links, 237–238
NoC switches, 238–239
test data transport, 239–241
transport time minimization,
241–244
multicast test scheduling, 244
unicast test scheduling, 242–244
Communication task graph (CTG), 308
Communication weighted model
(CWM), 137
Complementary metal oxide
semiconductor (CMOS)
technology, 63, 77, 156, 317
Concentrated mesh (CMESH)
topology, 16
Index
Asynchronous FIFO design, 54–56
dual-clock, 56f
FIFO memory, 56f
scalable gray code concept, 55, 55f
Automated test equipment (ATE), 245
Automated test pattern generation
(ATPG), 239
Average overall latency (L avg ), 80
under localized traffic
in 3D NoC with self-similar
traffic, 342–345, 342t, 343f, 344f
in MoT with VC router, 110–111,
110f, 111f, 112f
MoT with WH router
at different locality factors,
86–87, 87f
under localized traffic, 99–101, 99t,
100f, 101f
B
Bandwidth (BW), 80
utilization, 311
Best effort (BE) service, 45–46
Best fit decreasing (BFD) heuristics, 247
BI Hamming (BIH) code, 223
Binary and gray coding scheme,
170, 170t
Binomial mapping (BMAP), 129
flowchart, 130f
OCN design flow in, 129f
stages of OCN synthesis process
in, 129
Bisection width, 75
Bit error (ε), probability, 228
Bit error rate (BER), 174, 228, 228f
Bose–Chaudhuri–Hocquenghem (BCH)
code, 220
Boundary shift code (BSC), 224
Built-in self-repair (BISR)
mechanism, 204
Built-in self-test (BIST), 254, 257
Built-in soft error resilience (BISER)
technique, 206
Burst word error, probability, 229
Bus-invert (BI) code, 168, 222
hardware of, 168, 169f
scheme with 8-bit data bus, 169t
Butterfly fat tree (BFT) network, 75, 325
2D, 21, 21f
3D, 333, 334f
distribution of cores, routers, and
links in, 77f
router classification, 76
C
Capacitive crosstalk avoidance
techniques
CAC, 212–216
driver strength, 211
increase inter-wire spacing, 211
OCS, 211–212
usage of shielding and duplicating
wire, 210, 211t
Channel direction control (CDC)
protocol, 311
Channel power consumption, 255
Channel width and flit size, selection, 84
Chip-Level Integration of
Communicating
Heterogeneous Elements
(CLICHÉ), 14–15
Chip multiprocessing (CMP)
system, 1, 9
Clustering-based approach, 276f
Communication cost (fitness), 282
Communication dependence
and computation model
(CDCM), 138
Communication fabric, testing, 236–244
NoC links, 237–238
NoC switches, 238–239
test data transport, 239–241
transport time minimization,
241–244
multicast test scheduling, 244
unicast test scheduling, 242–244
Communication task graph (CTG), 308
Communication weighted model
(CWM), 137
Complementary metal oxide
semiconductor (CMOS)
technology, 63, 77, 156, 317
Concentrated mesh (CMESH)
topology, 16