Index
Note: Locators followed by “f” and “t” denote figures and tables in the text
3D integrated circuit (3D IC), 317
clock distribution structures for,
321, 321f
n-layer
cross section of stacked layers,
319, 320f
heat dissipation in, 319, 320f
NoC topologies on, 323, 323f
3D integration, 318–322
challenges of, 321–322
CAD tools, 322
interconnect design, 321–322
reliability, 322
thermal effects, 321
opportunities of, 319–321
decrease in interconnect
length, 319
heterogeneous and
multifunctional SoC design,
319, 321
3D NoC architecture, design and
evaluation of, 323–350
application-specific traffic,
simulation results with,
349–350, 350t
hand mapping of cores, 349, 349t
MoT topology
2 × 4 × 4, 327f
average distance, 327–330
number of directed edges, 326
properties, 326
performance and cost evaluation,
331–340
network area estimation, 336, 337t,
338, 339t
network aspect ratio, 339–340, 340t
self-similar traffic, simulation results
with
accepted traffic vs. offered load,
340–341, 341f
energy consumption, 345–349,
346f, 346t, 347t, 348t
L avg under localized traffic,
342–345, 342t, 343f, 344f
throughput vs. locality factor,
341–342, 341t
1500 wrapper, 246, 247f
A
ACK/NACK flow control protocol,
44, 45f
Adaptive router architecture design,
70–73
Adaptive voltage scaling (AVS), 160
Aggressor lines, 81, 237
Ant colony optimization (ACO), 123
Application Specific Integrated Circuit
(ASIC), 290
Application-specific NoC (ASNoC), 263
literature survey, 265–267
synthesis problem, 264–265
synthesis with flexible router
placement, see ASNoC
synthesis with flexible router
placement
Architecture-aware analytic mapping
algorithm (A3MAP), 149
ASNoC synthesis with flexible router
placement, 277–284
communication trace graph, 277f
ILP for
constraints, 279–281
objective function, 279
variables, 278–279
PSO for
evolution of generation, 283
local and global bests, 282
particle structure and fitness
function, 282
swap operator, 283
swap sequence, 283–284
router locations, 277f
routers at corners, 277f
359
Note: Locators followed by “f” and “t” denote figures and tables in the text
3D integrated circuit (3D IC), 317
clock distribution structures for,
321, 321f
n-layer
cross section of stacked layers,
319, 320f
heat dissipation in, 319, 320f
NoC topologies on, 323, 323f
3D integration, 318–322
challenges of, 321–322
CAD tools, 322
interconnect design, 321–322
reliability, 322
thermal effects, 321
opportunities of, 319–321
decrease in interconnect
length, 319
heterogeneous and
multifunctional SoC design,
319, 321
3D NoC architecture, design and
evaluation of, 323–350
application-specific traffic,
simulation results with,
349–350, 350t
hand mapping of cores, 349, 349t
MoT topology
2 × 4 × 4, 327f
average distance, 327–330
number of directed edges, 326
properties, 326
performance and cost evaluation,
331–340
network area estimation, 336, 337t,
338, 339t
network aspect ratio, 339–340, 340t
self-similar traffic, simulation results
with
accepted traffic vs. offered load,
340–341, 341f
energy consumption, 345–349,
346f, 346t, 347t, 348t
L avg under localized traffic,
342–345, 342t, 343f, 344f
throughput vs. locality factor,
341–342, 341t
1500 wrapper, 246, 247f
A
ACK/NACK flow control protocol,
44, 45f
Adaptive router architecture design,
70–73
Adaptive voltage scaling (AVS), 160
Aggressor lines, 81, 237
Ant colony optimization (ACO), 123
Application Specific Integrated Circuit
(ASIC), 290
Application-specific NoC (ASNoC), 263
literature survey, 265–267
synthesis problem, 264–265
synthesis with flexible router
placement, see ASNoC
synthesis with flexible router
placement
Architecture-aware analytic mapping
algorithm (A3MAP), 149
ASNoC synthesis with flexible router
placement, 277–284
communication trace graph, 277f
ILP for
constraints, 279–281
objective function, 279
variables, 278–279
PSO for
evolution of generation, 283
local and global bests, 282
particle structure and fitness
function, 282
swap operator, 283
swap sequence, 283–284
router locations, 277f
routers at corners, 277f
359