Index
361
Constructive heuristics
for application mapping, 128–134
binomial merging iteration,
130–131, 132f
hardware cost optimization,
132–134
topology mapping and traffic
surface creation, 131–132
with iterative improvement, 134–141
initialization phase, 134–135
iterative improvement phase,
136–137
other constructive strategies,
137–141
shortest path computation,
135–136
Core graph, 120
Cores, testing, 245–260
core wrapper design, 246–250
1500 wrapper, 246, 247f
algorithm, 249t
two wrappers, 248f
heuristic algorithms, 253–258
ILP formulation, 250–253
PSO-based strategy
evolution of generations, 259–260
particle structure and fitness,
258–259, 259f
Crosstalk avoidance and double error
correction (CADEC) codes,
226–227, 226f
Crosstalk avoidance code (CAC), 210,
212
FOC, 212–213, 213t
FPC, 214–215
FTC, 213–214
OLC, 216
Crosstalk delay, 197
to MAF model, 195, 196f
types of, 199t
Custom interconnection topology and
route generation, 271–277
constraints, 274–277
latency, 276
node-to-port mapping, 274
port capacity, 274
port-to-port mapping, 274
traffic routing, 274–276
objective function, 273–274
router allocation for, 272f
variables
derived, 273
independent, 272–273
Cyclic redundancy check (CRC), 217
Cyclic redundancy codes (CRCs), 218
D
DAP bus-invert (DAPBI) code, 227
Data link layer, 4
Deep submicron (DSM) technology, 75,
191, 237, 317
of n interconnects, 167, 167f
Design-for-testability (DfT) logic, 246
Discrete PSO (DPSO) technique,
mapping using, 141–149
augmentations to, 144–149
convergence of DPSO, 143
evolution of generations, 142–143
overall PSO algorithm, 144
particle structure, 141–142, 142f
Double error detection (DED) codes, 220
Double-switching errors, 198, 198f
false/double clocking due to, 199f
Drain-to-source current (I DS ), 157
Duato’s protocol, 41
Duplicate-add-parity (DAP) code, 224
Dynamic adaptive–deterministic
(DyAD) routing, 70–73, 71f
Dynamic frequency scaling (DFS), 155
architecture of, 180f
in system-level power reduction,
179–185
characteristics, 184t
DFS algorithm, 183
history-based DFS, 181–182,
182f, 184t
link controller, 183–184
Dynamic voltage and frequency scaling
(DVFS), 160
Dynamic voltage scaling (DVS), 155,
172–179
characteristics, 173
components of links, 173f
hardware implementation, 178, 178f
history-based, 174–178
361
Constructive heuristics
for application mapping, 128–134
binomial merging iteration,
130–131, 132f
hardware cost optimization,
132–134
topology mapping and traffic
surface creation, 131–132
with iterative improvement, 134–141
initialization phase, 134–135
iterative improvement phase,
136–137
other constructive strategies,
137–141
shortest path computation,
135–136
Core graph, 120
Cores, testing, 245–260
core wrapper design, 246–250
1500 wrapper, 246, 247f
algorithm, 249t
two wrappers, 248f
heuristic algorithms, 253–258
ILP formulation, 250–253
PSO-based strategy
evolution of generations, 259–260
particle structure and fitness,
258–259, 259f
Crosstalk avoidance and double error
correction (CADEC) codes,
226–227, 226f
Crosstalk avoidance code (CAC), 210,
212
FOC, 212–213, 213t
FPC, 214–215
FTC, 213–214
OLC, 216
Crosstalk delay, 197
to MAF model, 195, 196f
types of, 199t
Custom interconnection topology and
route generation, 271–277
constraints, 274–277
latency, 276
node-to-port mapping, 274
port capacity, 274
port-to-port mapping, 274
traffic routing, 274–276
objective function, 273–274
router allocation for, 272f
variables
derived, 273
independent, 272–273
Cyclic redundancy check (CRC), 217
Cyclic redundancy codes (CRCs), 218
D
DAP bus-invert (DAPBI) code, 227
Data link layer, 4
Deep submicron (DSM) technology, 75,
191, 237, 317
of n interconnects, 167, 167f
Design-for-testability (DfT) logic, 246
Discrete PSO (DPSO) technique,
mapping using, 141–149
augmentations to, 144–149
convergence of DPSO, 143
evolution of generations, 142–143
overall PSO algorithm, 144
particle structure, 141–142, 142f
Double error detection (DED) codes, 220
Double-switching errors, 198, 198f
false/double clocking due to, 199f
Drain-to-source current (I DS ), 157
Duato’s protocol, 41
Duplicate-add-parity (DAP) code, 224
Dynamic adaptive–deterministic
(DyAD) routing, 70–73, 71f
Dynamic frequency scaling (DFS), 155
architecture of, 180f
in system-level power reduction,
179–185
characteristics, 184t
DFS algorithm, 183
history-based DFS, 181–182,
182f, 184t
link controller, 183–184
Dynamic voltage and frequency scaling
(DVFS), 160
Dynamic voltage scaling (DVS), 155,
172–179
characteristics, 173
components of links, 173f
hardware implementation, 178, 178f
history-based, 174–178