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Three-Dimensional Integration of Network-on-Chip
consideration. From performance side, due to lesser interconnection links,
the throughput of 3D BFT and 3D Mesh-2 networks will be lesser under uniformly distributed and low localized traffic.
11.3.4 Simulation results with Application-Specific Traffic
For evaluating the MoT network under real benchmark application, this
chapter considers a DVOPD application consisting of 32 cores where two
VOPDs are running in parallel. The core graph of DVOPD application has
been shown in Chapter 4. Due to unavailability of mapping algorithm in the
literature for 3D NoC structures, this chapter uses hand mapping of cores
for all the 3D NoCs taken here into consideration. Table 11.10 shows the hand
mapping of cores with their names and coordinates.
The performance and cost of MoT network is evaluated and compared
with other networks taken here into consideration. Here, traffic generation
is done in a self-similar manner. However, the communication requirements
of the tasks in the application have been taken into consideration. The total
traffic generated per unit time confirms with the bandwidth requirement
specified for the edges of the task graph.
In the simulation, the parameters such as packet length, flit size, link
width, core size, and operating frequency of the networks are taken as same
as before. Table 11.11 presents the simulation results of different 3D NoC
structures. As the average overall latencies of all the topologies are well
below the network saturation point, it can be stated that the injection loads
to the network are less. Figure 11.16 shows that at low offered load, router
energy dominates over the link energy. Thus, due to low offered load and
high-connectivity routers in Mesh-1 network, its energy consumption is the
highest. From the simulation results, it can be stated that the hand mapping solution for MoT is comparable with the other 3D NoC structures.
TABLe 11.10
Hand Mapping of Cores in Four-Layered 3D SoC
Cores Mapped in Different Active Silicon Layers
Coordinate
Layer 0
Layer 1
Layer 2
Layer 3
0,0
vop mem1
arm2
vld2
ac/dc pred2
0,1
vop rec1
sh mem2
sh mem1
stripe mem2
0,2
down samp2
arith dec1
inv scan1
idct2
0,3
arith dec2
pad2
rld1
iquant2
1,0
pad1
arm1
vld1
rld2
1,1
mem2
down samp1
stripe mem1
inv scan2
1,2
up samp1
vop rec2
ac/dc pred1
mem1
1,3
idct1
vop mem2
iquant1
up samp2