Clock tree
Clock root
Clock root
Tiers
Tiers
Clock tree
321
Three-Dimensional Integration of Network-on-Chip
functionality or by combining different technologies. Currently,
SoC solutions limit designers to one fabrication technology for
both analog and digital circuits. Usage of 3D ICs allows integrating the best technology for a particular portion of an application
into the chip cube (Davis et al. 2005). In a typical 3D SoC, optical devices, analog circuitry, and digital circuitry can be implemented in separate layers. This defining feature of 3D ICs offers
unique opportunities for highly heterogeneous and multifunctional systems.
11.2.2 Challenges of 3D integration
• Thermal effects: One of the major concerns in 3D IC design is thermal effects. Although shorter interconnect length causes decrease
in power consumption, the power density is more in 3D IC compared to that in 2D IC due to lesser footprint area. As the power
density increases, the temperature of those planes not adjacent
to the heat sink of the package will rise. Each 10°C increase in
operating temperature increases delay by almost 5%. Doubling
the heat density without any improvement in cooling capacity
will lead to more than 30% degradation in performance (Davis
et al. 2005). While performance benefit is the major aspect in 3D
IC, performance degradation due to temperature increment is the
main bottleneck.
• Interconnect design: In 3D IC, due to integration of different
fabrication process or disparate technologies in different layers, interconnect design is the major design challenge in 3D IC.
In these diverse systems, global interconnect such as clock distribution grows in interest. Figure 11.2 shows different clock
distribution structures for 3D IC-based systems. In Figure 11.2a,
Figure 11.2
Clock distribution structures for 3D IC-based systems. (a) H-Tree is at each layer of 3D IC;
(b) H-Tree is at ground layer of 3D IC.